Superconducting quantum logic and applications of same

ABSTRACT

A superconducting logic cell includes at least one quantum phase-slip junction (QPSJ) for receiving at least one input and responsively providing at least one output, each QPSJ being configured such that when an input voltage of an input voltage pulse exceeds a critical value, a quantized charge of a Cooper electron pair tunnels across said QPSJ as an output, when the input voltage is less than the critical value, no quantized charge of the Cooper electron pair tunnels across said QPSJ as the output, where the presence and absence of the quantized charge in the form of a constant area current pulse in the output form two logic states, and the at least one QPSJ is biased with a bias voltage. The superconducting logic cell further includes at least one Josephson junction (JJ) coupled with the at least one QPSJ to perform one or more logic operations.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application claims priority to and the benefit of, pursuant to 35U.S.C. §119(e), U.S. Provisional Patent Application Ser. No. 62/347,165,filed Jun. 8, 2016, which is incorporated herein in its entirety byreference.

Some references, which may include patents, patent applications andvarious publications, are cited and discussed in the description of thisinvention. The citation and/or discussion of such references is providedmerely to clarify the description of the present invention and is not anadmission that any such reference is “prior art” to the inventiondescribed herein. All references cited and discussed in thisspecification are incorporated herein by reference in their entiretiesand to the same extent as if each reference was individuallyincorporated by reference. In terms of notation, hereinafter, “[n]”represents the nth reference cited in the reference list. For example,[32] represents the 32th reference cited in the reference list, namely,Uday S Goteti and Michael C Hamilton, Spice model implementation ofquantum phase-slip junctions, Electronics Letters, 51(13):979-981, 2015.

FIELD OF THE INVENTION

The present invention relates generally to superconducting quantumlogic, and more particularly, to charge-based logic using quantumphase-slip junctions (QPSJs) and complementary quantum logic (CQL) usingQPSJs and Josephson junctions (JJs), and their applications.

BACKGROUND OF THE INVENTION

The background description provided herein is for the purpose ofgenerally presenting the context of the present invention. The subjectmatter discussed in the background of the invention section should notbe assumed to be prior art merely as a result of its mention in thebackground of the invention section. Similarly, a problem mentioned inthe background of the invention section or associated with the subjectmatter of the background of the invention section should not be assumedto have been previously recognized in the prior art. The subject matterin the background of the invention section merely represents differentapproaches, which in and of themselves may also be inventions. Work ofthe presently named inventors, to the extent it is described in thebackground of the invention section, as well as aspects of thedescription that may not otherwise qualify as prior art at the time offiling, are neither expressly nor impliedly admitted as prior artagainst the present invention.

Superconducting electronics, primarily involving Josephson junctions andrelated devices have been crucial in several analog and digitalelectronic applications, as well as in quantum computing. With thereport of Josephson junctions (JJ), it was quickly realized that thesedevices can be used advantageously as significantly fast switches andlogic devices compared to conventional CMOS based logic [1-3]. Avoltage-state type logic was pursued in earlier developments at IBM, forexample, which used zero-voltage of JJs during its superconducting stateas logical ‘0’ and corresponding non-zero voltage of its normal state aslogical ‘1’ [4, 5]. This logic family found difficulty competing withCMOS logic due to several disadvantages including poor choice ofsuperconducting materials, and mainly, the use of under-damped Josephsonjunctions that latch into the voltage state, once switched [6], althoughseveral improvements were suggested [7, 8]. Some of the drawbacks of avoltage-state logic family were addressed using single flux quantum(SFQ) logic, which employs over-damped JJs, was introduced in 1985 [9]and was experimentally demonstrated in 1987 [10]. Later, severalimprovements were suggested for circuits in this logic family [11-13].

Rapid single-flux-quantum (RSFQ) logic family is known to performarithmetic and logic operations at compellingly high clock speeds (a fewhundred GHz) [14, 15] using significantly lower energy compared toexisting CMOS technologies [16-19]. The basic logic elements of thistechnology employ superconducting loops, broken with JJs, that storeflux quanta as its basic logic element. The state of the element can bemeasured as voltage pulses with quantized area [6]. However, RSFQ logichas disadvantages in having static power dissipation and in requiringrelatively large DC current biases to supply current to all thejunctions, which, in-turn, introduce difficulties in design. These twodisadvantages were overcome by other related technologies that use thesame quantized flux logic but with improved biasing techniques such aslow voltage RSFQ [19, 20], energy-efficient RSFQ (ERSFQ/eSFQ) [17, 18,21], reciprocal quantum logic (RQL) [22, 23] and adiabatic quantum fluxparametron (AQFP) [24, 25].

Quantum phase-slip is a phenomenon in superconducting systems where thephase difference between two connected superconducting regions changesby 2π with the suppression of the superconducting order parameter tozero. This occurs with quantum tunneling of vortices or fluxons across anarrow superconducting line, which is a dual to macroscopic quantumtunneling of charges across the insulating barrier in Josephson junctionstructures [26]. These effects have been studied extensively forquasi-one-dimensional nano-wires , with thermally induced phase slipsobserved near the superconducting transition temperatures of thenano-wire and quantum phase-slips at significantly lower temperatures[39-46]. Qubits based on coherent quantum phase-slips were proposed [45]and coherent phase-slip events were observed [44].

QPSJ-based structures may serve as a potential circuit element inapplications in superconducting electronics, quantum informationprocessing and as a current standard. However, demonstrating a QPSJ withproper DC and RF operation has been relatively challenging to implementpractically [46]. There has been no platform to identify potentialapplications of a QPSJ in electronic circuits.

Therefore, a heretofore unaddressed need exists in the art to addressthe aforementioned deficiencies and inadequacies.

SUMMARY OF THE INVENTION

One of the objectives of the present invention is to provide a new logicfamily, based on current pulses with quantized area of 2e, as that ofthe charge of a Cooper pair in a superconductor, using devices known asquantum phase-slip junctions (QPSJ). In certain embodiments, these logiccircuits are demonstrated using a SPICE model developed for a QPSJ. QPSJis treated in simulation in a fashion similar to a Josephson junction,which has been identified as its dual device based on charge-fluxduality. Example modes of operation of QPSJ-based structures in adigital logic circuit are established, based on exploring a range ofdevice parameters. Operation of the charge-based logic family is thendemonstrated using SPICE simulations.

Another objective of the present invention is to provide complementaryquantum logic (CQL) that uses QPSJs and JJs to form superconductingdigital logic circuits. Quantum phase-slips are identified as exactduals of Josephson junctions based on flux-charge duality. Based on theexisting flux-quantum logic circuits using JJs, complementary quantum(flux-charge) logic includes the use of charge and flux interactionscreating a new direction for logic circuit applications. In certainembodiments, SPICE model for a QPSJs is developed. Using the model andexisting JJ model, various embodiments of charge-based logic circuitsand CQL circuits are ddeveloped. These models are simulated in a circuitcomprising both JJs and QPSJs (i.e., a hybrid JJ/QPSJ circuit), todemonstrate operation of the circuits.

In one aspect, the present invention relates to a superconducting logiccell. In one embodiment, the superconducting logic cell includes atleast one QPSJ for receiving at least one input and responsivelyproviding at least one output, each QPSJ being configured such that whenan input voltage of an input voltage pulse exceeds a critical value, aquantized charge of a Cooper electron pair tunnels across said QPSJ asan output, when the input voltage is less than the critical value, noquantized charge of the Cooper electron pair tunnels across said QPSJ asthe output, where the presence and absence of the quantized charge inthe output form two logic states, and the at least one QPSJ is biasedwith a bias voltage.

In one embodiment, the bias voltage is about 50-95% of the criticalvoltage, the input voltage is at least about 110% of the criticalvoltage for quantized charge tunneling.

In one embodiment, each QPSJ is characterizable as a compact circuitmodel for SPICE implementation, where the compact circuit model includesa voltage source, a QPSJ, an inductor representing an inductance of anano-wire of the QPSJ, and a non-linear resistor that can have differentvalues of resistance in different phases of operation and showing normalto superconductor transition as a function of the voltage across theQPSJ, coupling to each other in series.

In one embodiment, the critical voltage, the inductance, and theresistance are determined by material properties and physical dimensionsof the QPSJ.

In one embodiment, the at least one QPSJ includes two QPSJs, where anode connecting two QPSJs and a capacitor defines a charge island. Inone embodiment the capacitor (or capacitance) may be a real, pysicalcomponent. In another embodiment, the capacitor (or capacitance) may bea parasitic capacitor, or just a property of the lines connecting theQPSJs.

In one embodiment, when the quantized charge of the Cooper electron pairtunnels across one of the two QPSJs, the quantized charge of the Cooperelectron pair is stored in the charge island, otherwise no quantizedcharge of the Cooper electron pair is stored in the charge island,thereby forming a basic logic element having the two logic states.

In one embodiment, the superconducting logic cell is a QPSJ transmissionline, where the at least one QPSJ includes a plurality of QPSJsconnected to one another in series, where each node connecting twoadjacent QPSJs and a capacitor defines a charge island.

In one embodiment, depending on the capacitance of the charge island andthe junction parameters, the quantized charge of the Cooper electronpair is either stored in a charge island or forced to hop to itsimmediately next charge island, thereby transferring the quantizedcharge of the Cooper electron pair along the QPSJ transmission line.

In one embodiment, amplification or attenuation of the current pulseamplitude is obtained by using QPSJs of different critical voltages anddifferent capacitor values.

In one embodiment, the superconducting logic cell is a QPSJ pulsesplitter comprising three QPSJs, where the first QPSJ has a firstterminal connected to an input voltage source defining an input node,and a second terminal connected to a first capacitor; the second QPSJhas a first terminal connected to the second terminal of the first QPSJ,and a second terminal connected to a second capacitor and a first biasvoltage source defining a first output node; and the third QPSJ has afirst terminal connected to the second terminal of the first QPSJ, and asecond terminal connected to a third capacitor and a second bias voltagesource defining a second output node. In operation, an input pulse atthe input node is split into two pulses output from the first and secondoutput nodes, respectively.

In one embodiment, the superconducting logic cell is a QPSJ buffercomprising three QPSJs, where the first QPSJ has a first terminalconnected to an input voltage source or a first bias voltage sourcedefining a first node, and a second terminal connected to a firstcapacitor defining a second node; the second QPSJ has a first terminalconnected to the second terminal of the first QPSJ defining a thirdnode, and a second terminal connected to a second capacitor and thefirst bias voltage source or the input voltage source defining a fourthnode; and the third QPSJ has a first terminal connected to the thirdnode, and a second terminal connected to a second bias voltage source.In operation, an input pulse from the first node through the first QPSJswitches to the third QPSJ, before it switches to the second QPSJ so asto prevent a signal flow in a direction from the first node to thefourth node, or when current arrives from an opposite direction, thefirst QPSJ switches before the third QPSJ, allowing the signal through.

In one embodiment, the superconducting logic cell is a QPSJ confluencebuffer comprising four QPSJs, where the first QPSJ has a first terminalconnected to a first input voltage source, and a second terminalconnected to a first capacitor defining node 3; the second QPSJ has afirst terminal connected to a second input voltage source, and a secondterminal connected to a second capacitor defining node 6, where bothnodes 3 and 6 are connected to node 7; the third QPSJ has a firstterminal connected to node 7, and a second terminal connected to a firstbias voltage source; and the fourth QPSJ has a first terminal connectedto node 7, and a second terminal connected to a third capacitor and thesecond bias voltage source at node 8. In operation, input pulses fromeither the first or second input voltage sources result in an outputpulse from node 8, but do not result in output from the other input.

In one embodiment, the superconducting logic cell is an RS flip-flop ora D flip-flop comprising two QPSJs, where the first QPSJ has a firstterminal connected to a bias voltage source at node 2 that in turn isconnected to a first input voltage source connected to node 1, a secondterminal is connected to node 3 that in turn is connected to acapacitor; and the second QPSJ has a first terminal connected to node 3,and a second terminal connected to node 4 that is in turn connected tothe second input voltage source. In one embodiment, the superconductinglogic cell is the RS flip-flop, where in operation, a SET input signalat node 1 induces a quantized charge of the Cooper electron pair to theisland of node 3, and a RESET input signal at node 4 induces a currentpulse in opposite direction to that induced by the SET input signal, soas to reset, or neutralize, the charge on the island, to perform afunction of an RS flip-flop. In one embodiment, the superconductinglogic cell is the D flip-flop, where in operation, a SET input signal atnode 1 induces a quantized charge of the Cooper electron pair to theisland of node 3, and a RESET input signal at node 4 is a clock signalthat switches the first QPSJ and induces a quantized charge of theCooper electron pair on the island, and with the next clock pulse, thecharge flows through an output terminal to perform a function of the Dflip-flop.

In one embodiment, the superconducting logic cell is a T flip-flopcomprising two QPSJs, where the first QPSJ has a first terminalconnected to a bias voltage source at node 3 that in turn is connectedto an input voltage source at node 2, the input voltage source connectedto node 1, a second terminal connected to node 4 that in turn isconnected to a capacitor; and the second QPSJ has a first terminalconnected to node 4, and a second terminal connected to node 2. Inoperation, a single clock signal of the input voltage source is input atnode 1, and at each clock pulse, the current pulse toggles from ON toOFF and vice versa, indicating the presence and absence of a quantizedcharge of the Cooper electron pair on the island with each clock pulse.

In one embodiment, the superconducting logic cell is a QPSJ based ORgate comprising six QPSJs, where the first to fourth QPSJs define theconfluence buffer and the fifth and sixth QPSJs define an island, wherethe confluence buffer is connected to the island in series such that afirst terminal of the fifth QPSJ is connected to the output terminal ofthe confluence buffer and a second terminal of the sixth QPSJ isconnected to a clock signal of a third input voltage source that isconnected to a second bias voltage source.

In one embodiment, the superconducting logic cell is a QPSJ based ANDgate comprising five QPSJs, where the first to fourth QPSJs define theconfluence buffer and the fifth QPSJ has a first terminal connected tothe output terminal of the confluence buffer and a second terminalconnected to a second bias voltage source, and the output terminal ofthe confluence buffer is connected to a clock signal of a third inputvoltage source that is connected to a second bias voltage source.

In one embodiment, the superconducting logic cell is a QPSJ based XORgate comprising four QPSJs, where the first to fourth QPSJs define theconfluence buffer and the output terminal of the confluence buffer isconnected to a clock signal of a third input voltage source that isconnected to a second bias voltage source.

In one embodiment, the superconducting logic cell further includes atleast one JJ coupled with the at least one QPSJ to perform one or morelogic operations, where each JJ is configured such that when an inputcurrent through said JJ exceeds a critical value, a single flux quantumpulse tunnels across said JJ as an output, when the input current isless than the critical value, no single flux quantum pulse tunnelsacross said JJ as the output, where the presence and absence of thesingle flux quantum pulse in the output form two logic states.

In one embodiment, the at least one QPSJ includes two QPSJs defining aQPSJ island with a capacitor, and the at least one JJ includes two JJsdefining a JJ loop with a inductor, and the QPSJ island and the JJ loopare connected in series to perform a bridge operation between flux andcharge.

In one embodiment, the at least one QPSJ further includes a third QPSJhaving a first terminal connected to a node between the QPSJ island andthe JJ loop, and a second terminal connected to a bias voltage source,where in operation, a voltage pulse is induced through the third QPSJthat enables or disables the output pulse. In another aspect, thepresent invention relates to a superconducting circuit device.

In one embodiment, superconducting circuit device includes at least onesuperconducting logic cell, each superconducting logic cell comprisingat least one QPSJ for receiving at least one input and responsivelyproviding at least one output, each QPSJ being configured such that whenan input voltage of an input voltage pulse exceeds a critical value, aquantized charge of a Cooper electron pair tunnels across said QPSJ asan output, when the input voltage is less than the critical value, noquantized charge of the Cooper electron pair tunnels across said QPSJ asthe output, where the presence and absence of the quantized charge inthe output form two logic states, and the at least one QPSJ is biasedwith a bias voltage.

In one embodiment, the at least one superconducting logic cell includesa charge island, a QPSJ transmission line, a QPSJ pulse splitter, a QPSJbuffer, a QPSJ confluence buffer, a QPSJ based OR gate, a QPSJ based ANDgate, a QPSJ based XOR gate, an RS flip-flop, a D flip-flop, a Tflip-flop, NOR, NAND, etc., or any combination thereof.

In one embodiment, the charge island is defined by a node connecting twoQPSJs and a capacitor.

In one embodiment, the QPSJ transmission line includes a plurality ofQPSJs connected to one another in series, where each node connecting twoadjacent QPSJs and a capacitor defines the charge island.

In one embodiment, the QPSJ pulse splitter includes three QPSJs, wherethe first QPSJ has a first terminal connected to an input voltage sourcedefining an input node, and a second terminal connected to a firstcapacitor; the second QPSJ has a first terminal connected to the secondterminal of the first QPSJ, and a second terminal connected to a secondcapacitor and a first bias voltage source defining a first output node;and the third QPSJ has a first terminal connected to the second terminalof the first QPSJ, and a second terminal connected to a third capacitorand a second bias voltage source defining a second output node. Inoperation, an input pulse at the input node is split into two pulsesoutput from the first and second output nodes respectively.

In one embodiment, the QPSJ buffer includes three QPSJs, where the firstQPSJ has a first terminal connected to an input voltage source or afirst bias voltage source defining a first node, and a second terminalconnected to a first capacitor defining a second node; the second QPSJhas a first terminal connected to the second terminal of the first QPSJdefining a third node, and a second terminal connected to a secondcapacitor and the first bias voltage source or the input voltage sourcedefining a fourth node; and the third QPSJ has a first terminalconnected to the third node, and a second terminal connected to a secondbias voltage source. In operation, an input pulse from the first nodethrough the first QPSJ switches to the third QPSJ, before it switches tothe second QPSJ so as to prevent a signal flow in a direction from thefirst node to the fourth node, or when current arrives from an oppositedirection, the first QPSJ switches before the third QPSJ, allowing thesignal through.

In one embodiment, the QPSJ confluence buffer includes four QPSJs, wherethe first QPSJ has a first terminal connected to a first input voltagesource, and a second terminal connected to a first capacitor definingnode 3; the second QPSJ has a first terminal connected to a second inputvoltage source, and a second terminal connected to a second capacitordefining node 6, where both nodes 3 and 6 are connected to node 7; thethird QPSJ has a first terminal connected to node 7, and a secondterminal connected to a first bias voltage source; and the fourth QPSJhas a first terminal connected to node 7, and a second terminalconnected to a third capacitor and the second bias voltage source atnode 8. In operation, input pulses from either the first or second inputvoltage sources result in output from node 8, but not to the otherinput.

In one embodiment, the QPSJ based OR gate includes six QPSJs, where thefirst to fourth QPSJs define the confluence buffer and the fifth andsixth QPSJs define an island, where the confluence buffer is connectedto the island in series such that a first terminal of the fifth QPSJ isconnected to the output terminal of the confluence buffer and a secondterminal of the sixth QPSJ is connected to a clock signal of a thirdinput voltage source that is connected to a second bias voltage source.

In one embodiment, the QPSJ based AND gate includes five QPSJs, wherethe first to fourth QPSJs define the confluence buffer and the fifthQPSJ has a first terminal connected to the output terminal of theconfluence buffer and a second terminal connected to a second biasvoltage source, and the output terminal of the confluence buffer isconnected to a clock signal of a third input voltage source that isconnected to a second bias voltage source.

In one embodiment, the QPSJ based XOR gate includes four QPSJs, wherethe first to fourth QPSJs define the confluence buffer and the outputterminal of the confluence buffer is connected to a clock signal of athird input voltage source that is connected to a second bias voltagesource.

In one embodiment, the RS flip-flop or the D flip-flop includes twoQPSJs, where the first QPSJ has a first terminal connected to a biasvoltage source at node 2 that in turn is connected to a first inputvoltage source connected to node 1, a second terminal connected node 3that in turn is connected to a capacitor; and the second QPSJ has afirst terminal connected to node 3, and a second terminal connected tonode 4 that is in turn connected to the second input voltage source.

In one embodiment, in operation, a SET input signal at node 1 induces aquantized charge of the Cooper electron pair to the island of node 3,and a RESET input signal at node 4 induces a current pulse opposite tothat induced by the SET input signal so as to reset, or neutralize, thecharge on the island to perform a function of the RS flip-flop.

In one embodiment, in operation, a SET input signal at node 1 induces aquantized charge of the Cooper electron pair to the island of node 3,and a RESET input signal at node 4 is a clock signal that switches thefirst QPSJ and induces a quantized charge of the Cooper electron pair onthe island, and with the next clock pulse, the charge flows through anoutput terminal to perform a function of the D flip-flop.

In one embodiment, the T flip-flop includes two QPSJs, where the firstQPSJ has a first terminal connected to a bias voltage source at node 3that in turn is connected to an input voltage source at node 2, theinput voltage source connected to node 1, a second terminal connectednode 4 that in turn is connected to a capacitor; and the second QPSJ hasa first terminal connected to node 4, and a second terminal connected tonode 2. In operation, a single clock signal of the input voltage sourceis input at node 1, and at each clock pulse, the current pulse togglesfrom ON to OFF and vice versa, indicating the presence and absence of aquantized charge of the Cooper electron pair on the island with eachclock pulse.

In one embodiment, the superconducting circuit device is a QPSJ basedhalf-adder comprising the AND and XOR gates along with splitters tosplit the input pulses to both the XOR and AND gates.

In one embodiment, the superconducting circuit device is a QPSJ basedshift register comprising a plurality of stages connected in series,each stage comprising the D flip-flop and having a different butidentical clock input.

In one embodiment, the superconducting circuit device is a QPSJ basedring counter comprising a plurality of flip-flop stages connected to oneanother in a ring.

In one embodiment, the superconducting circuit device is a QPSJ basedOR-AND circuit.

In one embodiment, the superconducting circuit device is a QPSJ basedring oscillator comprising two QPSJ transmission lines, a confluencebuffer and a pulse splitter, where the confluence buffer is connected tothe first QPSJ transmission lines that in turn is connected to the pulsesplitter, the pulse splitter is connected to the second QPSJtransmission lines that in turn is connected to the confluence buffer.

In one embodiment, the superconducting circuit device further includesat least one CQL cell, each CQL cell comprising at least one QPSJ, andat least one JJ coupled with the at least one QPSJ to perform one ormore logic operations, where each JJ is configured such that when aninput current through said JJ exceeds a critical value, a single fluxquantum pulse tunnels across said JJ as an output, when the inputcurrent is less than the critical value, no single flux quantum pulsetunnels across said JJ as the output, where the presence and absence ofthe single flux quantum pulse in the output form two logic states.

In one embodiment, the CQL cell includes two QPSJs defining a QPSJisland with a capacitor, and two JJs defining a JJ loop with a inductor,and the QPSJ island and the JJ loop are connected in series to perform abridge operation between flux and charge.

In one embodiment, the CQL cell further includes a third QPSJ having afirst terminal connected to a node between the QPSJ island and the JJloop, and a second terminal connected to a bias voltage source, where inoperation, a voltage pulse is induced through the third QPSJ thatenables or disables the output pulse.

In yet another aspect, the invention relates to a superconductingcircuit device comprising at least one of one or more Josephsonjunctions and one or more quantum phase slip junctions.

These and other aspects of the present invention will become apparentfrom the following description of the preferred embodiment taken inconjunction with the following drawings, although variations andmodifications therein may be affected without departing from the spiritand scope of the novel concepts of the disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings illustrate one or more embodiments of thepresent invention and, together with the written description, serve toexplain the principles of the invention. Wherever possible, the samereference numbers are used throughout the drawings to refer to the sameor like elements of an embodiment.

FIG. 1 shows a compact circuit model for a QPSJ implemented in a SPICEmodel according to one embodiment of the present invention.

FIG. 2 shows a QPSJ circuit for simulation with piece-wise linearfunction for voltage V from −1.2 mV to 1.2 mV in 4 ns and seriesresistor R=100Ω, according to one embodiment of the present invention.

FIG. 3 shows current-voltage (I-V) characteristics of the QPSJ circuitshown in FIG. 2, according to one embodiment of the present invention,which is simulated in JSPICE using relevant model parameters.

FIG. 4 shows I-V characteristics of the compact circuit model of theQPSJ shown in FIG. 1 with V_(C)=1 mV, L=20 nH and R=1 kΩ, according toone embodiment of the present invention.

FIG. 5 shows design parameter evaluation for InOx, where the shadedregion shows design parameter combinations satisfying conditions forforming a QPSJ, according to one embodiment of the present invention.

FIG. 6 shows design parameter evaluation for NbN, where the shadedregion shows design parameter combinations satisfying conditions forforming a QPSJ, according to one embodiment of the present invention.

FIG. 7 shows I-V characteristics of InOx based QPSJ simulated in WRSPICEwith V_(C)=14.7 mV, R=300 kΩ, L=2.8 nH, according to one embodiment ofthe present invention.

FIG. 8 shows I-V characteristics of NbN based QPSJ simulated in WRSPICEwith V_(C)=2.94 mV, R=37.2 kΩ, L=14.24 nH, according to one embodimentof the present invention.

FIG. 9 shows switching characteristics of a QPSJ according to oneembodiment of the present invention, which demonstrates a quantized-areacurrent pulse (with a value=2e) for charge-based logic for two materialsystems.

FIG. 10 shows switching dynamics of QPSJ (a) and (b), and of JJ (c) and(d).

FIG. 11 shows rapid single-flux-quantum (RSFQ) and QPSJ based logic: (a)loop storing flux Φ₀ in RSFQ based logic, (b) and (c) island storingcharge 2e in QPSJ based logic according to one embodiment of the presentinvention.

FIG. 12 shows a QPSJ transmission line comprising a pluarity of QPSJswith a DC voltage bias of 4×0.7V_(C) and pulse input signal according toone embodiment of the present invention, where V_(C) is the criticalvoltage of each of the junctions. Hereinafter, a QPSJ may be denoted bya capital letter “Q” in the disclosure.

FIG. 13 shows simulation results of the QPSJ transmission lineillustrating charge 2e traveling across islands according to oneembodiment of the present invention: (a) current at node 1, (b) currentat node 2, and (c) current at node 3. The QPSJ transmission line isshown in FIG. 12.

FIG. 14 shows simulation results of the QPSJ transmission line withmultiple pulses according to one embodiment of the present invention:(a) current at node 1, (b) current at node 2, and (c) current at node 3.The QPSJ transmission line is shown in FIG. 12.

FIG. 15 shows a pulse splitter according to one embodiment of thepresent invention, where the critical voltage of Q1 is 0.7 Vc, and thecritical voltages of Q2 and Q3 are Vc.

FIG. 16 shows simulation result of the pulse splitter circuit shown inFIG. 15 according to one embodiment of the present invention: (a) totalinput voltage signal at node 1, (b) current at node 1, (c) current atnode 3, and (d) current at node 4.

FIG. 17 shows two buffer circuits (a) and (b) showing current flowsituations in both directions according to embodiments of the presentinvention, where the critical voltage of Q1=0.7 Vc, the critical voltageof Q2 is Vc, and the critical voltage of Q3 is 1.4 Vc. FIG. 18 showssimulation results of the buffer circuit shown in FIG. 17(a) accordingto one embodiment of the present invention: (a) signal at node 1, (b)signal through Q3, and (c) signal at node 4.

FIG. 19 shows simulation results of the buffer circuit shown in FIG.17(b) according to one embodiment of the present invention: (a) signalat node 1, (b) signal through Q3, and (c) signal at node 4.

FIG. 20 shows a QPSJ merger according to one embodiment of the presentinvention, where the critical voltages of Q1 and Q2 are 1.4 Vc, thecritical voltages of Q3 is Vc, and the critical voltages of Q4 is 0.7Vc.

FIG. 21 shows simulation results of the QPSJ merger shown in FIG. 20according to one embodiment of the present invention: (a) total inputvoltage signal at node 1, (b) current pulse at node 3, (c) current pulseat node 6, and (d) output signal at node 8.

FIG. 22 shows an RS flip-flop using QPSJs forming an island with acapacitor according to one embodiment of the present invention, wherethe critical voltages of Q1 and Q2 are V_(C), and C=1.5 V_(C)/2e.

FIG. 23 shows simulation results for RS flip-flop circuit shown in FIG.22 according to one embodiment of the present invention: (a) inputvoltage pulse at SET, i.e., node 1, (b) input voltage pulse at RESET,i.e., node 4, and (c) output current pulse at node 4.

FIG. 24 shows a T flip-flop circuit obtained from QPSJ island and clockinput according to one embodiment of the present invention, where thecritical voltages of Q1 and Q2 is V_(C), and C=1.5V_(C)/2e.

FIG. 25 shows simulation results for the T flip-flop shown in FIG. 24according to one embodiment of the present invention: (a) clock signalinput at node 1, and (b) output current signal coming out of node 2.

FIG. 26 shows a QPSJ based OR gate formed by combining a confluencebuffer and an RS flip-flop according to one embodiment of the presentinvention.

FIG. 27 shows simulation results of the OR gate implemented using QPSJsshown in FIG. 26 according to one embodiment of the present invention:(a) input current pulse at node 1, (b) input current pulse at node 2,and (c) output current pulse at node 9.

FIG. 28 shows an AND gate circuit implemented by replacing the RSflip-flop in the OR gate with a buffer circuit according to oneembodiment of the present invention.

FIG. 29 shows simulation results of the AND gate implemented using QPSJsshown in FIG. 28 according to one embodiment of the present invention:(a) input current pulse at node 1, (b) input current pulse at node 2,and (c) output current pulse at node 8.

FIG. 30 shows an XOR gate circuit implemented by removing the buffercircuit in the AND gate according to one embodiment of the presentinvention.

FIG. 31 shows simulation results of XOR gate implemented using QPSJsshown in FIG. 30 according to one embodiment of the present invention:(a) input current pulse at node 1, (b) input current pulse at node 2,and (c) output current pulse at node 8.

FIG. 32 shows a half-adder circuit according to one embodiment of thepresent invention.

FIG. 33 shows simulation results of the half-adder using the XOR and ANDgates shown in FIG. 32 according to one embodiment of the presentinvention, (a) input A, (b) input B, (c) sum (node S), and (d) carry(node C).

FIG. 34 shows a 4-stage shift register using the D flip-flops accordingto one embodiment of the present invention.

FIG. 35 shows simulation results of shift register shown in FIG. 34according to one embodiment of the present invention: (a) input datapulses, (b) output after stage 1, (c) output after stage 2, and(d)output after stage 3.

FIG. 36 shows a ring counter using D flip-flops according to oneembodiment of the present invention.

FIG. 37 shows simulation results of the ring counter shown in FIG. 36according to one embodiment of the present invention: (a) output afterstage 1, (b) output after stage 2, (c) output after stage 3, and (d)output after stage 4.

FIG. 38 shows an OR-AND logic circuit according to one embodiment of thepresent invention.

FIG. 39 shows simulation results of the OR-AND gate shown in FIG. 38according to one embodiment of the present invention: (a) input A, (b)input B, (c) input C, (d) input D, and (e) output F.

FIG. 40 shows a block diagram of a QPSJ based ring oscillator accordingto one embodiment of the present invention.

FIG. 41 shows simulation results of the ring oscillator shown in FIG. 40according to one embodiment of the present invention.

FIG. 42 shows power dissipated per switching event in an InOx QPSJ for anano-wire of length 1 μm according to one embodiment of the presentinvention.

FIG. 43 shows switching speed in an InOx QPSJ for a nano-wire of length1 μm according to one embodiment of the present invention.

FIG. 44 shows power and switching delay comparison between QPSJ, singleflux quantum and reciprocal quantum logic circuits according to oneembodiment of the present invention.

FIG. 45 shows a circuit of single-flux-quantum loop and quantized chargeisland in series facilitating flux-charge conversion according to oneembodiment of the present invention.

FIG. 46 shows simulation of the circuit shown in FIG. 45 demonstratingflux-charge conversion according to one embodiment of the presentinvention.

FIG. 47 shows a control/buffer circuit using flux-charge elementsenabling logic operation in complementary quantum logic (CQL) accordingto one embodiment of the present invention.

FIG. 48 shows output signal generation enabled by control signal at thecontrol/buffer circuit shown in FIG. 47 according to one embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsof the present invention are shown. The present invention may, however,be embodied in many different forms and should not be construed aslimited to the embodiments set forth herein. Rather, these embodimentsare provided so that this disclosure will be thorough and complete, andwill fully convey the scope of the invention to those skilled in theart. Like reference numerals refer to like elements throughout.

The terms used in this specification generally have their ordinarymeanings in the art, within the context of the invention, and in thespecific context where each term is used. Certain terms that are used todescribe the invention are discussed below, or elsewhere in thespecification, to provide additional guidance to the practitionerregarding the description of the invention. For convenience, certainterms may be highlighted, for example using italics and/or quotationmarks. The use of highlighting and/or capital letters has no influenceon the scope and meaning of a term; the scope and meaning of a term arethe same, in the same context, whether or not it is highlighted and/orin capital letters. It will be appreciated that the same thing can besaid in more than one way. Consequently, alternative language andsynonyms may be used for any one or more of the terms discussed herein,nor is any special significance to be placed upon whether or not a termis elaborated or discussed herein. Synonyms for certain terms areprovided. A recital of one or more synonyms does not exclude the use ofother synonyms. The use of examples anywhere in this specification,including examples of any terms discussed herein, is illustrative onlyand in no way limits the scope and meaning of the invention or of anyexemplified term. Likewise, the invention is not limited to variousembodiments given in this specification.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a,” “an,” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise.

It will be understood that when an element is referred to as being “on,”“attached” to, “connected” to, “coupled” with, “contacting,” etc.,another element, it can be directly on, attached to, connected to,coupled with or contacting the other element or intervening elements mayalso be present. In contrast, when an element is referred to as being,for example, “directly on,” “directly attached” to, “directly connected”to, “directly coupled” with or “directly contacting” another element,there are no intervening elements present. It will also be appreciatedby those of skill in the art that references to a structure or featurethat is disposed “adjacent” to another feature may have portions thatoverlap or underlie the adjacent feature.

It will be understood that, although the terms first, second, third,etc. may be used herein to describe various elements, components,regions, layers and/or sections, these elements, components, regions,layers and/or sections should not be limited by these terms. These termsare only used to distinguish one element, component, region, layer orsection from another element, component, region, layer or section. Thus,a first element, component, region, layer or section discussed below canbe termed a second element, component, region, layer or section withoutdeparting from the teachings of the present invention.

Furthermore, relative terms, such as “lower” or “bottom” and “upper” or“top,” may be used herein to describe one element's relationship toanother element as illustrated in the figures. It will be understoodthat relative terms are intended to encompass different orientations ofthe device in addition to the orientation shown in the figures. Forexample, if the device in one of the figures is turned over, elementsdescribed as being on the “lower” side of other elements would then beoriented on the “upper” sides of the other elements. The exemplary term“lower” can, therefore, encompass both an orientation of lower andupper, depending on the particular orientation of the figure. Similarly,if the device in one of the figures is turned over, elements describedas “below” or “beneath” other elements would then be oriented “above”the other elements. The exemplary terms “below” or “beneath” can,therefore, encompass both an orientation of above and below.

It will be further understood that the terms “comprise(s)” and/or“comprising,” or “include(s)” and/or “including” or “has (have)” and/or“having” or “contain(s)” and/or “containing” when used in thisspecification specify the presence of stated features, regions,integers, steps, operations, elements, and/or components, but do notpreclude the presence or addition of one or more other features,regions, integers, steps, operations, elements, components, and/orgroups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which the present invention belongs. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and thepresent disclosure, and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

As used herein, “around,” “about,” “substantially” or “approximately”shall generally mean within 20 percent, preferably within 10 percent,and more preferably within 5 percent of a given value or range.Numerical quantities given herein are approximate, meaning that theterms “around,” “about,” “substantially” or “approximately” can beinferred if not expressly stated.

As used herein, the terms “capacitor” and “capacitance” areinterchangeable in the disclosure, and may refer to a real, pysicalcomponent, a parasitic capacitor, or just a property of the linesconnecting the QPSJs.

As used herein, the phrase at least one of A, B, and C should beconstrued to mean a logical (A or B or C), using a non-exclusive logicalOR. It should be understood that one or more steps within a method maybe executed in different order (or concurrently) without altering theprinciples of the present disclosure. As used herein, the term “and/or”includes any and all combinations of one or more of the associatedlisted items.

The description is now made as to the embodiments of the invention inconjunction with the accompanying drawings. Although various exemplaryembodiments of the present invention disclosed herein may be describedin the context of superconducting quantum logic that have significantadvantages primarily in energy consumption and ease offabrication/design, it should be appreciated that aspects of the presentinvention disclosed herein are not limited to being used in connectionwith one particular type of charged-based logic using quantum phase-slipjunctions (QPSJs) and complementary quantum logic (CQL) using QPSJs andJosephson junctions (JJs) and may be practiced in connection with othertypes of charged-based logic and CQL or other types of logic devicesusing charged-based logic and CQL without departing from the scope ofthe present invention disclosed herein.

In one aspect of the invention, the superconducting logic cell includesat least one QPSJ for receiving at least one input and responsivelyproviding at least one output, each QPSJ being configured such that whenan input voltage of an input voltage pulse exceeds a critical value, aquantized charge of a Cooper electron pair tunnels across said QPSJ asan output, when the input voltage is less than the critical value, noquantized charge of the Cooper electron pair tunnels across said QPSJ asthe output, where the presence and absence of the quantized charge inthe output form two logic states, and the at least one QPSJ is biasedwith a bias voltage. In one embodiment, the bias voltage is about 70-80%of the critical voltage, the input voltage is at least about 150% of thecritical voltage for quantized charge tunneling. It should beappreciated by those having ordinary skill in the art that other rangesof the bias voltage and the input voltage can also be utilized topractice the invention.

Referring to FIG. 1, each QPSJ is characterizable as a compact circuitmodel for SPICE implementation. The compact circuit model comprises avoltage source V, a QPSJ element, an inductor L representing aninductance of a nano-wire of the QPSJ, and a non-linear resistor Rhaving different values of resistance in different phases of operationand showing normal to superconductor transition as a function of thevoltage across the QPSJ, coupling to each other in series.

As discussed below, the critical voltage, the inductance, and theresistance are determined by material properties and physical dimensionsof the QPSJ.

In one embodiment, the at least one QPSJ comprises two QPSJs, where anode connecting two QPSJs and a capacitor defines a charge island, asshown in FIGS. 11(b) and 11(c). In one embodiment the capacitor may be areal, pysical component. In another embodiment, the capacitor may be aparasitic capacitor, or just a property of the lines connecting theQPSJs. When the quantized charge of the Cooper electron pair tunnelsacross one of the two QPSJs, the quantized charge of the Cooper electronpair is stored in the charge island, otherwise no quantized charge ofthe Cooper electron pair is stored in the charge island, thereby forminga basic logic element having the two logic states.

As shown in FIG. 12, in this exemplary embodiment, the superconductinglogic cell is a QPSJ transmission line, where the at least one QPSJcomprises four QPSJs connected to one another in series, where each nodeconnecting two adjacent QPSJs and a capacitor defines a charge island.According to the invention, the quantized charge of the Cooper electronpair is stored in a change island or forced to hop to its immediatelynext charge island, by proper design or tuning of a capacitance of thecharge island, along with the junction parameters, thereby transferringthe quantized charge of the Cooper electron pair along the QPSJtransmission line. In certain embodiments, amplification or attenuationof the current pulse amplitude is obtained by using the QPSJs ofdifferent critical voltages and different capacitor values.

In one embodiment, as shown in FIG. 15, the superconducting logic cellis a QPSJ pulse splitter that comprises three QPSJs, where the firstQPSJ has a first terminal connected to an input voltage source definingan input node, and a second terminal connected to a first capacitor; thesecond QPSJ has a first terminal connected to the second terminal of thefirst QPSJ, and a second terminal connected to a second capacitor and afirst bias voltage source defining a first output node; and the thirdQPSJ has a first terminal connected to the second terminal of the firstQPSJ, and a second terminal connected to a third capacitor and a secondbias voltage source defining a second output node. In operation, aninput pulse at the input node is split into two pulses output from thefirst and second output nodes respectively.

In one embodiment, as shown in FIG. 15, the superconducting logic cellis a QPSJ buffer including three QPSJs, where the first QPSJ has a firstterminal connected to an input voltage source or a first bias voltagesource defining a first node, and a second terminal connected to a firstcapacitor defining a second node; the second QPSJ has a first terminalconnected to the second terminal of the first QPSJ defining a thirdnode, and a second terminal connected to a second capacitor and thefirst bias voltage source or the input voltage source defining a fourthnode; and the third QPSJ has a first terminal connected to the thirdnode, and a second terminal connected to a second bias voltage source.In operation, an input pulse from the first node through the first QPSJswitches to the third QPSJ, before it switches to the second QPSJ so asto prevent a signal flow in a direction from the first node to thefourth node, or when current arrives from an opposite direction, thefirst QPSJ switches before the third QPSJ, allowing the signal through.

In one embodiment, as shown in FIG. 20, the superconducting logic cellis a QPSJ confluence buffer having four QPSJs, where the first QPSJ hasa first terminal connected to a first input voltage source, and a secondterminal connected to a first capacitor defining node 3; the second QPSJhas a first terminal connected to a second input voltage source, and asecond terminal connected to a second capacitor defining node 6, whereboth nodes 3 and 6 are connected to node 7; the third QPSJ has a firstterminal connected to node 7, and a second terminal connected to a firstbias voltage source; and the fourth QPSJ has a first terminal connectedto node 7, and a second terminal connected to a third capacitor and thesecond bias voltage source at node 8. In operation, input pulses fromeither the first or second input voltage sources result in an outputpulse from node 8, but do not result in output from the other input.

In one embodiment, as shown in FIG. 22, the superconducting logic cellis an RS flip-flop or a D flip-flop comprising two QPSJs, where thefirst QPSJ has a first terminal connected to a bias voltage source atnode 2 that in turn is connected to a first input voltage sourceconnected to node 1, a second terminal connected to node 3 that in turnis connected to a capacitor; and the second QPSJ has a first terminalconnected to node 3, and a second terminal connected to node 4 that isin turn connected to the second input voltage source.

In one embodiment, the superconducting logic cell is the RS flip-flop.In operation, a SET input signal at node 1 induces a quantized charge ofthe Cooper electron pair to the island of node 3, and a RESET inputsignal at node 4 induces a current pulse opposite to that induced by theSET input signal so as to reset the charge on the island.

In one embodiment, the superconducting logic cell is the D flip-flop. Inoperation, a SET input signal at node 1 induces a quantized charge ofthe Cooper electron pair to the island of node 3, and a RESET inputsignal at node 4 is a clock signal that switches the first QPSJ andinduces a quantized charge of the Cooper electron pair on the island,and with the next clock pulse, the charge flows through an outputterminal to perform a function of the D flip-flop.

In one embodiment, as shown in FIG. 24, the superconducting logic cellis a T flip-flop comprising two QPSJs, where the first QPSJ has a firstterminal connected to a bias voltage source at node 3 that in turn isconnected to an input voltage source at node 2, the input voltage sourceconnected to node 1, a second terminal connected node 4 that in turn isconnected to a capacitor; and the second QPSJ has a first terminalconnected to node 4, and a second terminal connected to node 2. Inoperation, a single clock signal of the input voltage source is input atnode 1, and at each clock pulse, the current pulse toggles from ON toOFF and vice versa, indicating the presence and absence of a quantizedcharge of the Cooper electron pair on the island with each clock pulse.

In one embodiment, as shown in FIG. 26, the superconducting logic cellis a QPSJ based OR gate comprising six QPSJs, where the first to fourthQPSJs define a confluence buffer and the fifth and sixth QPSJs define anisland, where the confluence buffer is connected to the island in seriessuch that a first terminal of the fifth QPSJ is connected to the outputterminal of the confluence buffer and a second terminal of the sixthQPSJ is connected to a clock signal of a third input voltage source thatis connected to a second bias voltage source.

In one embodiment, as shown in FIG. 28, the superconducting logic cellis a QPSJ based AND gate comprising five QPSJs, where the first tofourth QPSJs define the confluence buffer and the fifth QPSJ has a firstterminal connected to the output terminal of the confluence buffer and asecond terminal connected to a second bias voltage source, and theoutput terminal of the confluence buffer is connected to a clock signalof a third input voltage source that is connected to a second biasvoltage source.

In one embodiment, as shown in FIG. 30, the superconducting logic cellis a QPSJ based XOR gate comprising four QPSJs, where the first tofourth QPSJs define the confluence buffer and the output terminal of theconfluence buffer is connected to a clock signal of a third inputvoltage source that is connected to a second bias voltage source.

In one embodiment, the superconducting logic cell further includes atleast one JJ coupled with the at least one QPSJ to perform one or morelogic operations, where each JJ is configured such that when an inputcurrent through said JJ exceeds a critical value, a single flux quantumpulse tunnels across said JJ as an output, when the input current isless than the critical value, no single flux quantum pulse tunnelsacross said JJ as the output, where the presence and absence of thesingle flux quantum pulse in the output form two logic states.

In one embodiment, as shown in FIG. 45, the at least one QPSJ comprisestwo QPSJs defining a QPSJ island with a capacitor, and the at least oneJJ comprises two JJs defining a JJ loop with a inductor, and the QPSJisland and the JJ loop is connected in series to perform a bridgeoperation between flux and charge.

In one embodiment, as shown in FIG. 47, the at least one QPSJ furthercomprises a third QPSJ having a first terminal connected to a nodebetween the QPSJ island and the JJ loop, and a second terminal connectedto a bias voltage source, where in operation, a voltage pulse is inducedthrough the third QPSJ that enables or disables the output pulse.

In another aspect, the present invention relates to a superconductingcircuit device. In one embodiment, superconducting circuit deviceincludes at least one superconducting logic cell, each superconductinglogic cell comprising at least one QPSJ for receiving at least one inputand responsively providing at least one output, each QPSJ beingconfigured such that when an input voltage of an input voltage pulseexceeds a critical value, a quantized charge of a Cooper electron pairtunnels across said QPSJ as an output, when the input voltage is lessthan the critical value, no quantized charge of the Cooper electron pairtunnels across said QPSJ as the output, where the presence and absenceof the quantized charge in the output form two logic states, and the atleast one QPSJ is biased with a bias voltage.

In some embodiments, the at least one superconducting logic cellcomprises a charge island, a QPSJ transmission line, a QPSJ pulsesplitter, a QPSJ buffer, a QPSJ confluence buffer, a QPSJ based OR gate,a QPSJ based AND gate, a QPSJ based XOR gate, an RS flip-flop, a Dflip-flop, a T flip-flop, NOR, NAND, etc., or any combination thereof.It should be appreciated by those having ordinary skill in the art thatthe gates/circuits can also be extended to perform logic with greaterthan two inputs, and to more complex processes according to embodimentsof the invention.

As shown in FIGS. 11(b) and 11(c), the charge island is defined by anode connecting two QPSJs and a capacitor.

In one embodiment, the QPSJ transmission line comprises a plurality ofQPSJs, e.g., 4 QPSJs shown in FIG. 12, connected to one another inseries, where each node connecting two adjacent QPSJs and a capacitordefines the charge island. In one embodiment the capacitor may be areal, pysical component. In another embodiment, the capacitor may be aparasitic capacitor, or just a property of the lines connecting theQPSJs.

In one embodiment, as shown in FIG. 15, the QPSJ pulse splittercomprises three QPSJs, where the first QPSJ has a first terminalconnected to an input voltage source defining an input node, and asecond terminal connected to a first capacitor; the second QPSJ has afirst terminal connected to the second terminal of the first QPSJ, and asecond terminal connected to a second capacitor and a first bias voltagesource defining a first output node; and the third QPSJ has a firstterminal connected to the second terminal of the first QPSJ, and asecond terminal connected to a third capacitor and a second bias voltagesource defining a second output node. In operation, an input pulse atthe input node is split into two pulses output from the first and secondoutput nodes respectively.

In one embodiment, as shown in FIGS. 17 (a) and (b), the QPSJ buffercomprises three QPSJs, where the first QPSJ has a first terminalconnected to an input voltage source or a first bias voltage sourcedefining a first node, and a second terminal connected to a firstcapacitor defining a second node; the second QPSJ has a first terminalconnected to the second terminal of the first QPSJ defining a thirdnode, and a second terminal connected to a second capacitor and thefirst bias voltage source or the input voltage source defining a fourthnode; and the third QPSJ has a first terminal connected to the thirdnode, and a second terminal connected to a second bias voltage source.In operation, an input pulse from the first node through the first QPSJswitches to the third QPSJ, before it switches to the second QPSJ so asto prevent a signal flow in a direction from the first node to thefourth node, or when current arrives from an opposite direction, thefirst QPSJ switches before the third QPSJ, allowing the signal through.

In one embodiment, as shown in FIG. 20, the QPSJ confluence buffercomprises four QPSJs, where the first QPSJ has a first terminalconnected to a first input voltage source, and a second terminalconnected to a first capacitor defining node 3; the second QPSJ has afirst terminal connected to a second input voltage source, and a secondterminal connected to a second capacitor defining node 6, where bothnodes 3 and 6 are connected to node 7; the third QPSJ has a firstterminal connected to node 7, and a second terminal connected to a firstbias voltage source; and the fourth QPSJ has a first terminal connectedto node 7, and a second terminal connected to a third capacitor and thesecond bias voltage source at node 8. In operation, input pulses fromeither the first or second input voltage sources result in an outputpulse from node 8, but do not result in output from the other input.

In one embodiment, as shown in FIG. 26, the QPSJ based OR gate comprisessix QPSJs, where the first to fourth QPSJs define the confluence bufferand the fifth and sixth QPSJs define an island, where the confluencebuffer is connected to the island in series such that a first terminalof the fifth QPSJ is connected to the output terminal of the confluencebuffer and a second terminal of the sixth QPSJ is connected to a clocksignal of a third input voltage source that is connected to a secondbias voltage source.

In one embodiment, as shown in FIG. 28, the QPSJ based AND gatecomprises five QPSJs, where the first to fourth QPSJs define theconfluence buffer and the fifth QPSJ has a first terminal connected tothe output terminal of the confluence buffer and a second terminalconnected to a second bias voltage source, and the output terminal ofthe confluence buffer is connected to a clock signal of a third inputvoltage source that is connected to a second bias voltage source.

In one embodiment, as shown in FIG. 30, the QPSJ based XOR gatecomprises four QPSJs, where the first to fourth QPSJs define theconfluence buffer and the output terminal of the confluence buffer isconnected to a clock signal of a third input voltage source that isconnected to a second bias voltage source.

In one embodiment, as shown in FIG. 22, the RS flip-flop or the Dflip-flop comprises two QPSJs, where the first QPSJ has a first terminalconnected to a bias voltage source at node 2 that in turn is connectedto a first input voltage source connected to node 1, a second terminalconnected node 3 that in turn is connected to a capacitor; and thesecond QPSJ has a first terminal connected to node 3, and a secondterminal connected to node 4 that is in turn connected to the secondinput voltage source.

In one embodiment, in operation, a SET input signal at node 1 induces aquantized charge of the Cooper electron pair to the island of node 3,and a RESET input signal at node 4 induces a charge opposite to thatinduced by the SET input signal so as to reset the charge on the island.

In one embodiment, in operation, a SET input signal at node 1 induces aquantized charge of the Cooper electron pair to the island of node 3,and a RESET input signal at node 4 is a clock signal that switches thefirst QPSJ and induces a quantized charge of the Cooper electron pair onthe island, and with the next clock pulse, the charge flows through anoutput terminal to perform a function of the D flip-flop.

In one embodiment, as shown in FIG. 24, the T flip-flop comprises twoQPSJs, where the first QPSJ has a first terminal connected to a biasvoltage source at node 3 that in turn is connected to an input voltagesource at node 2, the input voltage source connected to node 1, a secondterminal connected node 4 that in turn is connected to a capacitor; andthe second QPSJ has a first terminal connected to node 4, and a secondterminal connected to node 2. In operation, a single clock signal of theinput voltage source is input at node 1, and at each clock pulse, thecurrent pulse toggles from ON to OFF and vice versa, indicating thepresence and absence of a quantized charge of the Cooper electron pairon the island with each clock pulse.

In one embodiment, as shown in FIG. 32, the superconducting circuitdevice is a QPSJ based half-adder comprising the AND and XOR gates alongwith splitters to split the input pulses to both the XOR and AND gates.

In one embodiment, as shown in FIG. 34, the superconducting circuitdevice is a QPSJ based shift register comprising a plurality of stagesconnected in series, each stage comprising the D flip-flop and having adifferent but identical clock input.

In one embodiment, as shown in FIG. 36, the superconducting circuitdevice is a QPSJ based ring counter comprising a plurality of stagesconnected to one another in a ring.

In one embodiment, as shown in FIG. 38, the superconducting circuitdevice is a QPSJ based OR-AND circuit.

In one embodiment, as shown in FIG. 40, the superconducting circuitdevice is a QPSJ based ring oscillator comprising two QPSJ transmissionlines, a confluence buffer and a pulse splitter, where the confluencebuffer is connected to the first QPSJ transmission lines that in turn isconnected to the pulse splitter, the pulse splitter is connected to thesecond QPSJ transmission lines that in turn is connected to theconfluence buffer.

In one embodiment, the superconducting circuit device further includesat least one CQL cell, each CQL cell comprising at least one QPSJ, andat least one JJ coupled with the at least one QPSJ to perform one ormore logic operations, where each JJ is configured such that when aninput current through said JJ exceeds a critical value, a single fluxquantum pulse tunnels across said JJ as an output, when the inputcurrent is less than the critical value, no single flux quantum pulsetunnels across said JJ as the output, where the presence and absence ofthe single flux quantum pulse in the output form two logic states.

In one embodiment, as shown in FIG. 45, the CQL cell comprises two QPSJsdefining a QPSJ island with a capacitor, and two JJs defining a JJ loopwith a inductor, and the QPSJ island and the JJ loop is connected inseries to perform a bridge operation between flux and charge.

In one embodiment, as shown in FIG. 47, the CQL cell further comprises athird QPSJ having a first terminal connected to a node between the QPSJisland and the JJ loop, and a second terminal connected to a biasvoltage source, where in operation, a voltage pulse is induced throughthe third QPSJ that enables or disables the output pulse.

In yet another aspect, the invention relates to a superconductingcircuit device comprising at least one of one or more Josephsonjunctions and one or more quantum phase slip junctions.

Without intent to limit the scope of the invention, exemplary methodsand their related results according to the embodiments of the presentinvention are given below. Note that titles or subtitles may be used inthe examples for convenience of a reader, which in no way should limitthe scope of the invention. Moreover, certain theories are proposed anddisclosed herein; however, in no way they, whether they are right orwrong, should limit the scope of the invention so long as the inventionis practiced according to the invention without regard for anyparticular theory or scheme of action.

Spice Model Implementation of QPSJ

In one aspect, the present invention relates to implementions of a dualto a resistively and capacitively shunted junction (RCSJ) based JJ SPICEmodel to model a QPSJ in JSPICE for exploration and demonstration ofcircuit operations of QPSJ devices. By means of a SPICE model developedfor quantum phase-slip junctions, switching of the island to producequantized-charge pulses with quantized area of 2e as that of the chargeof a Cooper pair in a superconductor is demonstrated. The mode ofoperation of a QPSJ is established, based on a range of deviceparameters.

Compact Model of QPSJ

Quantum phase-slip is a superconducting phenomenon where the phasedifference across a nano-wire changes by 2π with the suppression ofsuperconducting order parameter to zero, that is, a temporary decay ofsuperconductivity in a continuous superconducting nanowire. This eventoccurring at a point in the nano-wire introduces a Coulomb blockade,i.e., blockade of current/electric charge through the wire essentiallybehaving like an insulator. The phase-slip event is caused by a quantumunit of magnetic flux tunneling across the nanowire through theinsulating substrate/layer on which the device is fabricated. This wasobserved as a resistance tail below superconducting transition inexperiments [26, 29, 47]. This phenomenon has been identified as a dualprocess to Josephson tunneling. While a charge tunnels between twosuperconducting regions across an insulating barrier in a Josephsonjunction (JJ), inducing a flux quantum in the corresponding loop, a QPSJcan be viewed as flux tunneling across a superconducting nano-wire(barrier for flux) creating a voltage drop at the ends of the wire. Theduality between Josephson tunneling and quantum phase-slip can becharacterized by the charge-flux relationship in Maxwell's equations.Therefore, a dual-device to a JJ, called a QPSJ, can be established.Accordingly, an I-V relationship of a QPSJ can be obtained by replacingphase by charge, current term by voltage term and capacitance term byinductance term [27]. The two equations that describe a QPSJ aretherefore given by:

$\begin{matrix}{V = {{V_{C}{\sin (q)}} + {L\frac{dI}{dt}} + {RI}}} & (1) \\{where} & \; \\{I = {\frac{2e}{2\; \pi}\frac{dq}{dt}}} & (2)\end{matrix}$

Here, V is the voltage across the junction, V_(C) is the criticalvoltage of the QPSJ, L is the geometric inductance of the QPSJ, I is thecurrent through the junction, R is the normal resistance of the QPSJ,and q is the charge equivalent in the QPSJ normalized to the charge of aCooper pair (2e) and the term

$\frac{1}{2\; \pi}$

to represent q as a phase corresponding to charge. Therefore, therelation of q to charge 2e is equivalent to relation of superconductingphase φ and flux quantum Φ₀, with e being charge of an electron. Inpractical implementation, the various parameters of the junction can bevaried by varying the physical dimensions and material of the junction.

The mathematical description above can be described in a circuit modelas shown in

FIG. 1. The first term in Eqn. (1), which represents voltage across aquantum phase-slip event, can be re-written to describe the device as acapacitor with kinetic capacitance C_(k), given by:

$\begin{matrix}{C_{k} = \frac{2e}{2\; \pi \; V_{C}{\cos (q)}}} & (3)\end{matrix}$

Hence, the circuit shown in FIG. 1 can be treated as a series RLCcircuit. An over-damped QPSJ for the charge-based logic family is thusanalogous to the JJ in RSFQ logic. From the circuit and the descriptiongiven by Eqns. (1) and (2), a damping parameter for a QPSJ is given by:

$\begin{matrix}{\beta_{L} = \frac{2\; \pi \; V_{C}L}{2{eR}^{2}}} & (4)\end{matrix}$

β_(L)<<1 indicates an over-damped junction and β_(L)>>1 represents anunder-damped junction. With β_(L)≈1, the junction is critically damped.

As shown in FIG. 1, the compact model for the QPSJ used for SPICEimplementation has a voltage source, a non-linear resistor that hasdifferent values of resistance in different phases of operation and alsoshows normal to superconductor transition as a function of the voltageacross the device, an inductor that represents the inductance of thenano-wire and the ideal QPSJ device in series.

The SPICE model described by the Eqns. (1) and (2) cannot sufficientlycalculate quantum behavior by itself, which is the key to the generationof digital logic bits based on quantized charge trapping between QPSJsas explained in detail below. To simulate the quantum behavior of thedevice, the time-steps for numerical calculations of differentialequations above must be limited to quantized values that are smallerthan the time scale corresponding to plasma frequency of the junction.The time-step limit At applied to the simulations of the SPICE model isgiven by.

$\begin{matrix}{{\Delta \; t} = \frac{0.1}{\left( {\frac{2\; \pi}{2e}\frac{V_{C}}{L}} \right)^{1/2}}} & (5)\end{matrix}$

This model is generic and is valid to simulate any device similar to aQPSJ with inductance and resistance values not necessarily correspondingto a valid set to experimentally increase the probability of highquantum phase-slip rate.

MNA Stamp and RHS Vector of QPSJ

In certain embodiments, modified nodal analysis (MNA) [48] is used inthe SPICE to solve the circuits to calculate nodal voltages as well asbranch currents of linear or non-linear devices for all types ofanalysis in the SPICE. All the devices are represented in the form givenby Eqn. (6). The MNA stamp and RHS vector valid for transient analysisof a QPSJ are thus obtained and are suitable for implementation in theSPICE. The inductor portion of the model is solved using a trapezoidalmethod and the non-linear resistor along with the ideal QPSJ equation issolved using a Newton-Raphson method. Convergence of the model isverified under different simulation conditions. The MNA stamp which is a3×3 matrix and an RHS vector of the device is given by Eqn. (7). Thethird row and third column of the matrix give the numerical solution forthe combination of inductor and an ideal QPSJ, while the other 2×2section of the equation represents the non-linear resistor.

$\begin{matrix}{\lbrack I\rbrack = {{\lbrack Y\rbrack \lbrack V\rbrack} + \lbrack{RHS}\rbrack}} & (6) \\{\begin{bmatrix}I_{3} \\I_{0} \\V\end{bmatrix} = {{\begin{bmatrix}g & {- g} & 1 \\{- g} & g & {- 1} \\1 & {- 1} & {\frac{{- 2}L}{\Delta} + {{V_{C}\left( \frac{2\; \pi}{2e} \right)}\left( \frac{\Delta}{2} \right){\cos \left( \frac{2\; \pi \; q_{L}}{2e} \right)}}}\end{bmatrix}\begin{bmatrix}V_{3} \\V_{0} \\I\end{bmatrix}} + {\quad\begin{bmatrix}{{- {G(I)}} + {gI}} \\{{G(I)} - {gI}} \\{{- {L\left( {I^{\prime} + \frac{{- 2}I_{L}}{\Delta}} \right)}} + {V_{C}\left\lbrack {{\left( \frac{2\; \pi}{2e} \right)\left( \frac{\Delta \; L}{2} \right){\cos \left( \frac{2\; \pi \; q_{L}}{2e} \right)}} + {\sin \left( \frac{2\; \pi \; q_{L}}{2e} \right)}} \right\rbrack}}\end{bmatrix}}}} & (7)\end{matrix}$

In this equation (7), G is the conductance of the junction correspondingto the resistance term in Eqn. (1). g is the first derivative of G withrespect to current I through the device. q_(L) is the charge in thedevice in previous iteration. I_(L) is the current through the device inprevious iteration. A is the time step, which is usually assigned by theSPICE programs but can be changed manually if required. V₃, V₀ and I₃,I₀ are the voltages and currents at nodes 3 and 0 of the circuit shownin FIG. 1, and V, I are the voltage across and the current through thejunction, respectively. The above equation (7) is therefore valid fortime domain calculations with each calculation representing an instantof the operation of the device.

SPICE Simulations of I-V Characteristics of QPSJ

Programs for the QPSJ model were developed in a programming language Cthat is compatible with JSPICE3 by using the above MNA stamp and RHSvector along with additional initial condition checks, voltage limitsfor operation of the device, calculation of required model parametersfrom user input parameters and convergence flags. These programs wereintegrated with JSPICE3 for application in circuit simulations withother electronic components, including JJs. QPSJ model parametersincluding length, critical voltage, inductance, and resistances(phase-slip and normal) are assigned as user changeable parameters.

In certain embodiments, the input parameters that can be controlled bythe user while performing QPSJ simulations are discussed, along with thedefault values that are assigned to these parameters when the user doesnot provide values for them.

Critical voltage: the default value for V_(C) is 700 μV. The range ofthe values that can be assigned to V_(C) is from 10 μV to 0.1V . Therange cannot be changed by the user. But it can be modified in theVerilog-A program. Below the critical voltage, the device has idealquantum phase-slip characteristics, along with geometric inductance ofthe device and a sub-gap resistance that might be caused due toquasi-particles. These parameters can however be set to zero and arediscussed later.

Initiall charge: the charge q is calculated from the current through thedevice from previous instant of time in transient analysis and is thetotal charge that has passed through the junction in time t till thatinstant. It is given by Eqn. (8) below:

q=q _(ic) +∫eI(t)dt

where I(t) is the current through the junction which is a function oftime and e is the charge of an electron, e=1.9625×10⁻¹⁹ Coulombs. Afunction exists in the WRSPICE, which performs numerical integrationwhen Eqn. (4) is presented. This is also valid for Verilog-A models. TheIn JSPICE however, a numerical analysis for the integration must beperformed manually by defining a time-step and multiplying current ateach instant by the time-step to calculate the total charge. q_(ic) isthe initial condition charge, that can be assigned by the user torepresent a charged device which can aid in convergence. It has adefault value of 0 and can take any value.

Inductance: this is the total inductance of the device as seen in secondterm of Eqn. (1). It can include both the geometrical and kineticinductance of the device and has a default value of 890 nH.

TABLE 1 Default parameters assigned for QPSJ in JSPICE Parameter UnitsDefault value Junction critical voltage Volts (V) 700 × 10⁻⁶ Junctioninductance Henry (H) 890 × 10⁻⁹ Normal state resistance Ohms (Ω) 1.6 ×10⁶ 

Table 1 provides the user parameters with their default values. Thesevalues are chosen to match measurements and simulation results fromreference [46]. A representative circuit with a voltage source, seriesresistor and a QPSJ in series shown in FIG. 2 has been simulated with apiece-wise linear function for voltage source of −1.2 mV to 1.2 mV in 4ns. The resultant I-V characteristics are shown in FIG. 3.

The transient I-V characteristics shown in FIG. 3 represent voltage atnode 1 and current through the QPSJ in FIG. 2. The device thereforeexhibits a phase-slip event with a quantum phase-slip voltage below thecritical voltage of 0.7 mV. This is denoted as region I in FIG. 3.

In this region, there is a very small current (about 10 pA) with avoltage pulse observed across the device below the superconductingtransition. In region II of the I-V characteristics shown in FIG. 3, asupercurrent is observed below the critical voltage with a small sub-gapresistance and increasing current until the current reaches the criticalcurrent density of the device.

When the current is above the critical current of the device (region IIIof the I-V characteristics shown in in FIG. 3), the I-V curverepresenting a resistor is observed with corresponding normal resistancevalue. Similar behavior is observed with a negative voltage across thedevice as the device model is designed to be insensitive to the voltagepolarity. The obtained I-V characteristics are similar to thecalculations performed and measurements made for the parameters in Table1 and in reference [46]. This verifies that the SPICE model is accurateunder these conditions and can perform transient analyses of QPSJs toenable studies of advanced circuit configurations.

Silimiar I-V characteristics of the compact circuit model of QPSJ shownin FIG. 1 are obtained in the SPICE simulation and illustrated in FIG.4, where V_(C)=1 mV, L=20 nH and R=1 kΩ. Note that a linear resistancefunction with a resistance value equal to the normal resistance of theQPSJ is used here.

These results clearly show that the QPSJ at at low voltages is a perfectinsulator.

Device Parameter Evaluation

The junction parameters used to obtain the I-V characteristics shown inFIG. 4 are somewhat arbitrary and, therefore, they may or may not beapplicable for a practical junction. These parameters depend on thematerial properties and physical dimensions of the device and haveconstraints depending on parameter values that can produce quantum-phaseslips. These constraints are detailed in [26, 49] in the form of modelsassociating various material and design parameters to characteristicenergies corresponding to quantum phase-slip processes.

The critical voltage V_(C) is related to the phase-slip energy by:

$\begin{matrix}{V_{C} = \frac{2\; \pi \; E_{s}}{2e}} & (9)\end{matrix}$

where E_(s) is the phase-slip energy, which can be calculated using themodel by Mooij et al. [9]. The normal resistance R is calculated fromnormal-state resistivity of the given material and physical dimensionsof the nano-wire that forms the QPSJ. The inductance L of the junctionis related to inductive energy E_(L), which is a function of normalresistance R and critical temperature of the material [49]. As explainedin [49], the parameters satisfying the condition 0.1≦α≦1, where

$\alpha = \frac{E_{s}}{E_{L}}$

are expected to be suitable for quantum phase-slip junctions.

Two different materials, among others hypothesized as suitable for QPSJs[44, 46, 49, 50], InOx and NbN, are considered for parameter evaluation.Values of a subset of design parameters satisfying the 0.1≦α≦1 conditionfor both materials are represented in FIGS. 5 and 6, respectively. Notethat there is a range of combinations of design parameters satisfyingthe conditions for the same materials.

By considering an InOx junction of length=3 μm, width=70 nm andthickness=20 nm from shaded region of FIG. 5, it is obtained that thedevice parameters of the critical voltage V_(C)=14.7 mV, normalresistance R=300 kΩ and inductance L=2.8 nH. Similarly, when consideringan NbN junction of length=3 μm, width=10 nm and thickness=5 nm, it isobtained that the device parameters of the critical voltage V_(C)=2.94mV, normal resistance R=37.2 kΩ and inductance L=14.24 nH. Theseparameters can be directly used with the QPSJ SPICE model in the WRSPICEto obtain I-V characteristics. These values are also used to computecircuit and bias parameters suitable for the junction to exhibitquantized switching characteristics, for use in logic operations, whenappropriate circuits are designed using these junctions.

Switching Characteristics and Current Pulses with Quantized Area of QPSJ

The QPSJ parameters computed in the previous section are used to obtainI-V characteristics of the corresponding junctions. FIG. 7 shows thecharacteristics of an InOx junction where V_(C)=14.7 mV, R=300 kΩ, L=2.8nH while FIG. 8 shows the characteristics of an NbN junction whereV_(C)=2.94 mV, R=37.2 kΩ, L=14.24 nH. The I-V characteristics areobtained by sweeping voltage across the junctions and measuring currentsin the WRSPICE. The Coulomb blockade characteristic of QPSJs [46, 49]are clearly shown at low voltages. Since the SPICE model is valid onlyfor transient analysis [23], the curves demonstrate oscillatorycharacteristics in some regions.

Since the QPSJ can be described as a dual to the Josephson junctionbased on flux-charge duality of Maxwell's equations, a quantized chargeoperation of the QPSJ can be predicted that can lead topractically-implementable logic device dual to the single-flux-quantum(SFQ) logic. When the QPSJ is in an appropriate operating region, aswitching event produces a current pulse with a quantized areacorresponding to a charge of a Cooper pair (2e) described by:

$\begin{matrix}{{\int{Idt}} = {{\int_{0}^{2\; \pi}{\frac{2e}{2\; \pi}{dq}}} = {{2e} = {3.204\mspace{14mu} \ldots \times 10^{- 19}\mspace{11mu} C}}}} & (10)\end{matrix}$

Based on the device model shown in FIG. 1 and described by Eqns. (1) and(2), the QPSJ is equivalent to a series RLC oscillator. This oscillatormust be over-damped in order to produce quantized-area switchingcharacteristics similar to a Josephson junction in SFQ logic [6].

Switching characteristics with a quantized-area current pulse aredemonstrated by exciting a circuit having a QPSJ below its criticalvoltage, using a short voltage pulse that drives the junction above itscritical voltage. Plots demonstrating quantized-area current pulses withquantized area equal to 2e, for both InOx and NbN junctions withparameters taken from FIGS. 7 and 8, are shown in FIG. 9. Thesejunctions are over-damped by default and do not require additionaldamping resistors in series. The integrated area under these curves isequal to 2e, demonstrating the proper charge pulse.

The single quantized charge-based logic uses short, pico-second, currentpulses as the basic logic signals. These current pulses have a quantizedarea under the curve, which represent the total charge traveled alongthe nano-wire. Therefore, the presence and absence of the current pulseform the two logic states, similar to the voltage pulse in RSFQ logic[6]. The quantized area under the current pulse curve is given by Eqn.(10).

From Eqn. (1), the charge of 2e corresponds to the immediate excitedenergy state of a fluxon tunneling across the nano-wire which is a QPSJ[26]. If the junction is over-damped (or critically damped), the totalcharge through the junction with a bias voltage slightly over V_(C) isrestricted to charge 2e through it, with further oscillations damped,without further excitations.

The treatment of charge variable q of a QPSJ is analogous to thetreatment of Josephson junction phase φ.

$\left. \frac{2e}{2\; \pi}\leftrightarrow{\frac{\Phi_{0}}{2\; \pi}\mspace{14mu} {or}\mspace{14mu} q}\leftrightarrow\varphi \right.$

In certain embodiments, numerical simulation results of a single currentpulse with area of 2e under the curve are shown in FIG. 10. Simulationof an RSFQ pulse is also presented for comparison. Both the junctionsare also simulated in under-damped (without a damping resistor) andover-damped (with a damping resistor) configurations. The circuit setupfor both under-damped and over-damped QPSJs include a voltage bias of0.7V_(C) and a pulse voltage input in series with a QPSJ. Addition of aseries resistor makes it over-damped. A similar setup has been used fora JJ, where a current bias of 0.7I_(C) and a current pulse driving it.Addition of a parallel resistor makes the junction over-damped.Simulation results for all the cases (over-damped and under-damped JJand QPS) are shown in FIG. 10.

FIG. 10 shows the quantized area current pulse of a QPSJ very similar tothe quantized area voltage pulse of a JJ, when both the junctions areover-damped. In under-damped state, both the junctions switch when theinput current or voltage goes above the critical current or the criticalvoltage values and are then latched in that state. This ischaracteristic of the hysteresis behavior of both the junctions, where,once switched to a resistive state above their respective criticalvoltages or currents, the junctions do not revert back to theirsuperconducting states until the bias across them is completely zero. Inthe under-damped switching behavior of a QPSJ shown in in FIG. 10, thecurrent across the junction is non-zero even after its switching statedue to the presence of a voltage bias and a quasi-particle resistanceacross the device.

With over-damped QPSJs, a quantized charge of 2e flows through thejunction, similar to the flux developed across a JJ. Therefore, as inRSFQ, where a loop made of JJs and an inductor stores one quantum offlux Φ₀, an island formed by two QPSJs and a capacitor can store quantumof charge 2e. An ideal QPSJ is similar to a tunnel barrier, andtherefore the node formed between two QPSJ devices is similar to anisland [43].

Using the SPICE model developed for a QPSJ, an operation mode of thedevice feasible for logic implementation is demonstrated in thesimulations. The device is based on the quantized-charge and is a dualto flux-based logic in SFQ circuits.

Charge-Based Superconducting Logic Using QPSJ

A QPSJ can be designed and operated in an appropriate configuration toproduce quantized-area current pulses demonstrating tunneling of aCooper pair at an instant. This is similar to a Josephson junctionproducing a constant area voltage pulse indicating movement of fluxquanta across them. This can be achieved by over-damping the plasmaoscillations of the junction. The QPSJ can be treated as a series RLCoscillator and a damping parameter β_(L) is given by Eqn. (4). Thejunction is under-damped if β_(L)>>1 and over-damped if β_(L)<<1. Inorder to produce quantized-area current pulses, the SPICE model andsimulation of QPSJ must be modified to recognize plasma oscillations ofthe junction. Therefore, the time-step in the device model must belimited to below the time corresponding to the plasma frequency. TheQPSJ model in WRSPICE is therefore modified to limit the time step givenby Eqn. (5).

A QPSJ may be designed to be either in under-damped or over-damped modeusing Eqn. 1 and by appropriate choice of material properties anddimensions. Analogous to an SFQ circuit, the island circuit is biasedwith a DC voltage source V_(b) as shown in FIG. 11(c). The DC voltagebiases both the junctions to 70% of their critical voltages andtherefore has a value of 140% of V_(C). An input square voltage pulse isprovided as V_(in), with sufficient magnitude, i.e., greater than 150%,to switch the junction.

When the junction is under-damped, the switching event causes thejunction to switch and latch to a normal state. A result from simulationof the island circuit with both junctions under-damped is shown in FIG.10(b), where the area under the curve is greater than 2e. A quantizedcharge pulse, with area under the curve 2e can be produced by usingover-damped junctions. This is achieved by adding a series resistor toeach of the junctions, thereby increasing the value of R in Eqn. (1).The simulation result of an over-damped junction is shown in FIG. 10(a),where the area is quantized to 2e.

In certain aspect, the invention relate to a quantum logic family thatis based on current pulses with the quantized area of 2e as that of thecharge of a Cooper pair in a superconductor, using devices known as aQPSJ. These logic circuits are demonstrated using a SPICE modeldeveloped for a QPSJ. The mode of operation of a QPSJ is established,based on a range of device parameters of the device and its SPICE model.The operation of the charge-based logic family is then demonstratedusing SPICE simulations.

In certain embodiments, charge-based logic is realized, similar toflux-based logic [6], using an island made of two QPSJs and a capacitor.The circuit description of both the SFQ loop and its dual, the islandformed by QPSJs are shown in FIG. 11. This island configuration (b) and(c) forms the basic logic element of the single quantized charge basedlogic. By arranging these islands in various configurations as shown inthe following sections, the current pulses can be manipulated,transmitted, split and merged, and various basic logic elements can beformed. All the circuit configurations are obtained from flux-chargeduality of both the devices, by replacing a loop with an island, currentsources with voltage sources and inductors with capacitors.

The QPSJ behavior can be compared to a parallel LCR(inductor-capacitor-resistor) oscillator for simplicity, althoughcertain elements of the junction show non-linear behavior. Whenoscillations are triggered by a voltage pulse, each oscillationcorresponds to tunneling of a Cooper pair, or two electrons across theinsulating barrier setup by a phase-slip. When appropriately damped, itis possible to limit the oscillations to one at a time. A dampingparameter is given by Eqn. (4), which aids the operation in over-dampedregion where quantized oscillations are possible.

The primary logic element for the charge-based logic family, which cangenerate and trap a Cooper pair, or two electrons, is an islanddeveloped using QPSJs shown in FIGS. 11(b) and 11(c). Each of thejunctions, acting as insulating barriers due to the phase-slip,separates node 1 from rest of the circuit, creating a charge island.

When the over-damped first QPSJ is triggered by an input voltage pulseV_(in), while being DC biased by V_(b), a Cooper pair tunnels across thefirst QPSJ on to the island at node 1. This can be observed insimulation as a short current pulse, the area of which is equal tocharge of two electrons, the simulation of which is shown in FIG. 10(a),which is simulation of quantized charge tunneling characterized byconstant-area current pulse through the island. Note that the biasvoltage V_(b), must be about 70-80% of the critical voltage V_(C) andthe input voltage pulse magnitude V_(in) must be at least about 150% ofthe critical voltage V_(C) for the quantized charge tunneling.

This pulse is the logic bit ‘1’ in the charge-based logic family, whilethe absence of it is the bit ‘0’, that occurs when the input pulsecannot trigger the quantized charge tunneling. Note that, due to thequantum behavior of the QPSJ, there can only be existence or absence ofthis pulse, and not partial pulses when inappropriately triggered. Also,the shape of the pulse can vary depending on input and designconditions, but the area under the curve remains constant.

When these islands are connected in series, a single input trigger pulsecan cause the electron pair to hop from an island to its next islandcreating a transmission line for transfer of bits. By suitably tuningthe capacitance C in FIG. 11(c), along with the junction parameters,charge can either be trapped on an island, or forced to hop to its nextisland. Using these design techniques, several logic gates are designed,including, but are not limited to, an AND gate, an OR gate, an XOR gate,an RS flip-flop, a D flip-flop, a T flip-flop, and so on, which alsolead to complicated circuits such as a shift register, a ringoscillator, an adder, and so on. Design methodology is adequatelydeveloped to confirm operations of sufficient number of logic circuitsthat together make universal logic operations possible. To illustratethis logic family, a few of exemplary circuits and simulations are shownbelow.

QPSJ Transmission Line

In one embodiment, a basic operation of QPSJ circuits is demonstrated bysimulating a QPSJ transmission line which propagates quantized charge of2e along the islands similar to that of Josephson transmission lines[9-11]. In one embodiment, a QPSJ transmission line have a plurality ofQPSJs formed of a series of islands with a voltage bias and inputvoltage signal. One embodiment of the QPSJ transmission line circuit isshown in FIG. 12, where Q1-Q4 are denated first to fourth QPSJs,respectively.

In the circuit, all the QPSJs have an equal critical voltage of V_(C). ADC voltage bias is used at node 5, the value of which is equal to4×0.7V_(C) to be able to bias all four QPSJs in series. Since each QPSJcannot conduct any current until the applied voltage is above itscritical voltage, the charge in the islands is zero at this instant.When the input pulse signal is applied, the first QPSJ (Q1) switches asthe voltage across it goes above the critical voltage of the QPSJ. Ifthe first QPSJ is over-damped, a charge of 2e is generated, which isstored on the first island, i.e., node 2 of FIG. 12. This charge in turngenerates a voltage across the second QPSJ (Q2) causing it to overcomeits critical voltage. Thus, the charge of 2e, or the current pulse withthe quantized area of 2e travels along the transmission line. Thesimulation results of this circuit with the input voltage and current ateach node are shown in FIG. 13. The simulation results with multiplecurrent pulses along the transmission line are shown in FIG. 14. In someembodiments, amplification or attenuation of the current pulse amplitudeis obtained by using QPSJs of different critical voltage and differentcapacitor values.

QPSJ Pulse Splitter

Fan-out is generally required for implementation of useful digitallogic. In one embodiment, the current pulses is split for fan out withthe help of a pulse splitter circuit shown in FIG. 15, which employscharge propagation in islands similar to a QPSJ transmission line,employing different sized junctions. In this circuit, the first QPSJ Q1has a critical voltage of 0.7V_(C), where V_(C) is the critical voltageof Q2 and Q3. Both the bias voltages are equal to 1.7V_(C). Withoutdecrease in the amplitude of the current pulse, the input pulse is splitinto two output pulses. The simulation results for this circuit areshown in FIG. 16.

QPSJ Buffer

In both the circuits shown above so far, the input and output pulses arereciprocal, i.e., the current, and hence the quantized charge 2e canflow in both directions. In one embodiment, a QPSJ buffer is designed,as shown in FIG. 17, and can prevent this reciprocity when introduced inthe transmission lines or in logic circuits. In the circuit, thecritical voltage of the QPSJ Q1 is 0.7V_(C), the critical voltage of theQPSJ Q2 is V_(C) and the critical voltage of the QPSJ Q3 is 1.4V_(C).Therefore, the current pulse from Q1 switches Q3, before it switches Q2and prevents signal flow in the direction from node 1 to node 4.Whereas, when current arrives from the opposite direction, as shown inFIG. 18, the QPSJ Q1 switches before Q3, allowing the signal through.The bias voltage at node 4 is equal to 1.5V_(C) to bias both Q1 and Q2.Q3 is biased using a different voltage source, the value of which isequal to 0.7V_(C). The simulation results for both situations are shownin FIGS. 18 and 19, respectively.

QPSJ Confluence Buffer

In one embodiment, a confluence buffer circuit is an extension of thebuffer circuit with two inputs and an output. This circuit can be usedto merge two signals and generate a corresponding output pulse withoutcurrent pulses from one input going to another input. This circuit isshown in FIG. 20. Here, Q1 and Q2 have the critical voltages of1.4V_(C), the critical voltage of Q3 is V_(C) and the critical voltageof Q4 is 0.7V_(C). The simulation result of this circuit is shown inFIG. 21.

The circuits discussed so far can be used to manipulate the currentpulses, control direction, fan-in and fan-out of signals. In the nextsections, basic flip-flops and other logic circuits is presented anddiscussed.

RS Flip-Flop/D Flip-Flop

An RS flip-flop or the DC squid of the SFQ logic family is a keycomponent which can be used in other higher level logic circuits. Thecorresponding configuration in charge-based logic has been implementedin a simplest possible circuit using QPSJs, which is an island formedbetween two QPSJs. In one embodiment, the circuit shown in FIG. 22includes two QPSJs forming an island with a capacitor along with voltagebiases and signals at its two terminals corresponding to RESET and SET.Both the junctions Q1 and Q2 have the critical voltages of V_(C). Thecapacitor between node 3 and ground has a value of 1.5V_(C)/2e, enablingit to store a charge corresponding to a single Cooper pair at theisland, when SET signal is applied. A DC voltage source biases both thejunctions. The input signal at SET, which is V_(pulse) at node 1,induces a charge of 2e to the island, and the input signal at RESET,which is V_(pulse) at node 4, induces charge opposite to SET andtherefore resets the charge on the island. The simulation resultsillustrating the function of this circuit are shown in FIG. 23.

In one embodiment, a D flip-flop can be implemented using a similarcircuit. The input at RESET is replaced by a clock signal. Therefore,the input signal switches the first junction and induces a charge 2e onthe island. With the next clock pulse, the charge flows through the OUTterminal in the circuit performing the function of a D flip-flop.

T Flip-Flop

In one embodiment, a T flip-flop is also implemented using a verysimilar circuit to RS flip-flop. Both the RESET and SET inputs areconnected to a single clock signal, with the bias voltage connected asshown in the circuit shown in FIG. 24. At each clock pulse, the currentpulse toggles from ON to OFF and vice-versa indicating the presence andabsence of charge on the island with each clock pulse. The simulationresults of the circuit are shown in FIG. 25. The output current pulse isvery similar to the output pulse of RS flip-flop circuit simulation.

QPSJ Based OR Gate

According to embodiments of the invention, any logic operation can beperformed by combining two or more basic elements discussed so far. AnOR gate can be formed by cascading a confluence buffer and an islandformed by QPSJs similar to an RS flip-flop in series. The junctions withthe same critical voltages as that of RS flip-flop and confluencebuffer. This implementation is identical to the RSFQ based OR gate. Thecircuit diagram is given in FIG. 26. This is a timed OR gate, and hencehas a clock input.

When one or both the inputs are high, the confluence buffer produces acurrent pulse corresponding to a charge of 2e at the island, which isthe input to the RS flip-flop. With the next clock pulse, the chargestored on the island can be seen in the current pulse at the output.When both the inputs are low, there is no charge flow through theoutput. The simulation result of this circuit is shown in FIG. 27.

QPSJ Based AND Gate

In one embodiment, an AND operation in charge-based logic is obtained byslightly modifying the OR gate. The confluence buffer part of thecircuit is still used here to have a buffered two-input gate, but theisland part of the circuit which operates as an RS flip-flop has beenreplaced with a buffer circuit from FIG. 17. At the output node, a clockhas been added in series with the DC bias which makes this circuit asynchronized AND gate. The clock is necessary for the operation of thisgate and a version without clocked gates has not been designed yet. Itis possible to extend these gate to more than two inputs by adjustingthe parameters of the junctions accordingly. The circuit is shown inFIG. 28 and the simulation results are shown in FIG. 29.

When either one of the inputs is high, the junction in the buffercircuit Q5 switches therefore ensuring the output to be low. When boththe inputs are high during the same clock period, only one of thejunctions are negated by the buffer circuit and the output is stillhigh.

QPSJ Based XOR Gate

In one embodiment, a two input XOR operation using charge-based logic isimplemented in a way very similar to the OR gate and the AND gatediscussed above. A confluence buffer is used for the two input pulsesand the additional buffer gate that has been included for AND operationhas been removed. This ensures two identical inputs cancel each otherout, but only a single pulse at either of the gates will not be affectedby a buffer circuit. The circuit is shown in FIG. 30 and the simulationresults are shown in FIG. 31.

QPSJ Based Half-Adder

In one embodiment, in order to demonstrate that these individual gatedesigns shown so far can be used to perform more complicated logicoperations, a half adder is demonstrated by combining the AND and XORgates along with splitters to split the input pulses to both XOR and ANDgates. FIG. 32 illustrates the schematic of the half-adder circuit. FIG.33 shows the simulation results of the two-input half-adder circuit.

QPSJ Based Shift Register

In one embodiment, a D flip-flop demonstrated in the previous section isused to construct a shift register with identical clocks at each stage.A block diagram demonstrating the entire circuit is shown in FIG. 34.The circuit has four shift stages with each stage using a different butidentical clock input. The simulation results of the shift register areshown in FIG. 35.

QPSJ Based Ring Counter

In one embodiment, a ring counter is constructed using the D flip-flopsin a very similar way as a shift register. A single input pulse isneeded to trigger the circuit. An identical clock triggers each stageand a counter operation is observed in the simulation results shown inFIG. 37. FIG. 36 shows the block diagram of the circuit being simulated.

QPSJ Based OR-AND Circuit

In one embodiment, an OR-AND circuit shown in FIG. 38 is implemented.The gates used in this circuits are all synchronized and therefore usean identical clock. This illustrates that any other higher-level logiccircuits for complicated operation can be implemented using charge-basedlogic. The simulation results of this circuit are shown in FIG. 39.

QPSJ Based Ring Oscillator

In one embodiment, the logic blocks discussed in the previous section istreated as the fundamental building blocks for the logic family beingdiscussed. The elements of these blocks can be combined to form morecomplicated circuits. To illustrate this, an example of ring oscillatoris implemented. FIG. 40 shows the block diagram for the ring oscillator.This is based on Josephson junction based ring oscillator [31]. Thecorresponding simulation result with a single voltage pulse inputtriggering the oscillations in the ring is shown in FIG. 41.

Low-Power High-Speed Superconducting Logic Device Using QSPJ

As discussed above, in certain embodiments, quantized-charge logicelements for digital logic circuits based on a superconducting islandformed using superconducting nano-wires, which are operated to exhibitquantum phase-slip phenomena are disclosed. These logic elements areshown in simulations to implement a quantized charge-based logic familyalternative to single-flux quantum logic family. By means of a SPICEmodel developed for quantum phase-slip junctions, switching of theisland to produce quantized-charge pulses is demonstrated. The prospectof lower power dissipation and faster switching compared to single-fluxquantum logic, along with advantage of essentially zero static powerdissipation, in a practically implemented circuit, is highlighted.

In this exemplary embodiment, a low-power high-speed superconductingswitch having a superconducting island circuit as shown in FIG. 10(c) isdemonstrated using simulations in WRSPICE using a previously-developedSPICE model of a quantum phase-slip junction.

In one embodiment, a superconducting switch having a superconductingisland circuit as shown in FIG. 11(c) can be designed to consume lesspower per switching event and with similar switching speed compared toJosephson junction based logic circuits. The additional advantage ofthese circuits is essentially zero static power dissipation as thejunctions is in a coulomb blockade condition when they are biased belowthe critical voltage. For a practical junction using InOx material, thepower per switching event and switching speed for given dimensions of anano-wire can be calculated using the phase-slip energy model developedby Mooij et al. [49]. Results from this analysis are shown in FIGS. 42and 43. A plot of power and delay of QPSJ based logic compared with thatfor SFQ logic and reciprocal quantum logic (RQL) families is provided inFIG. 44, showing that QPSJ-based logic may exhibit competitivepower-delay properties.

In certain embodiments, a logic element using QPSJs is introduced toform a superconducting island, which is a dual to a loop in SFQcircuits, to perform quantized charge based logic. It is also shown,through simulation, that it is possible to design and control theswitching configuration of the devices, which can enable the design ofbasic logic circuits. Potential advantages of using this logic familyinclude reduced power consumption and fast switching speed, along withessentially zero static power dissipation. Estimates of powerdissipation and switching speed for a circuit that can be practicallyimplemented are provided.

Parameter Margin Analysis of Charge-Based Logic Circuits

Quantum phase-slip junctions, because of their extremely small junctiondimensions and parameters values like critical voltage, kineticcapacitance and voltage bias required for each island, can pose achallenge in circuit design if the parameter margins are small. Hence,worst case analysis of parameters of an island and a series of islandsas that of a QPSJ transmission line has been performed to determine thefeasibility of practical implementation charge-based logic circuits thatare presented here. The margins are found to be up to 30% on parameterslike normal resistance of the junction, kinetic capacitance and theseries damping resistance, but only 10% on inductance and bias voltage.In several cases, adjusting the bias voltage is sufficient to make thecircuit function as expected. The parameter margins depend on thecircuit design and can vary, but in principle, the charge-based logiccircuits can be designed have similar parameter margins as RSFQ basedcircuits. All the circuits that are presented here have junction sizesand switching parameters in common, and therefore are therefore expectedto have parameter margins of up to 30% on all their parameters exceptbias voltage and inductance of nano-wire.

Advantages of Charge-Based Logic over RSFQ

As disclosed in the logic circuits discussed so far, QPSJ based logic isvery similar to RSFQ logic, with the relation coming from flux-chargeduality. This logic is implemented using voltage bias in place ofcurrent biases as in RSFQ, therefore eliminating the need to supply biascurrents and thus significantly reducing the circuit complexity. Thismay also reduce static power consumption as current bias is eliminated.Furthermore, this logic family is compatible with RSFQ logic givingpossibilities to combine both charge-based and flux-based operation in asingle circuit. Further advantages of the QPSJ based logic include, butare not limited to, essentially zero static power dissipation,simplicity of fabrication (e.g., nano-wire of a single layer), possibleto design circuits dissipating lower energy compared to superconductingflux quantum based circuits without compromising on speed of operation.

QPSJs, the dual devices to JJs, are established as the basic logicdevices to implement single-quantized charge-based logic family. A SPICEmodel and other essential tools are developed to demonstrate basic logicelements. Most of the building block elements are designed with thebasis of charge on an island formed by QPSJs, and discussed using SPICEsimulations. These existing blocks can be combined and the idea can befurther extended to form other complicated logic blocks to completelyestablish superconducting charge-based logic.

The example simulations shown using a resistive and inductive seriesjunction (RLSJ) based lumped element SPICE model of a quantum phase-slipjunction in representative circuits verify the implementation and basicfunctionality of the model. This allows us to explore possibleapplications of superconducting electronic circuits based on QPSJs.Furthermore, this model and simulation capability opens avenues toexplore hybrid circuits with both JJs and QPSJs and may also be used toexplore possible methods to experimentally test quantum phase-slipjunctions.

Complementary Quantum Logic (CQL)

Complementary quantum logic involves combination of JJ-basedsingle-flux-quantum and QPSJ-based charge-based logic families.Therefore, the basic logic elements include the charge-island and acurrent loop producing quantized flux developed using JJs, as shown inFIG. 11. The logic operations in this family are performed bymanipulation of both quantized flux and charge characterized byconstant-area voltage pulse and constant-area current pulserespectively. In addition to individual logic operations, the use ofthese logic elements as bridges between single-flux-quantum logic familyand charge-based logic family are also disclosed according toembodiments of the invention.

In certain embodiments, the logic circuit including the JJ-loop andQPSJ-island is shown in FIG. 45, which demonstrates the bridge operationbetween flux and charge. The simulation showing flux to chargeconversion is shown in FIG. 46.

In certain embodiments, the logic operation is implemented with theaddition of a control/buffer element made of QPSJ to the flux-chargeconversion circuit shown in FIG. 45. A voltage pulse is induced throughthis control element that enables or disables the output pulse, i.e.,the voltage pulse (flux) at the input JJ loop gets converted to chargeisland at the output, contingent up on the control signal at the secondQPSJ essentially behaving as a switch. This operation requires propertuning of QPSJ parameters and capacitance values in the circuits. Thecontrol/buffer circuit is shown in FIG. 47. The simulation results areshown in FIG. 48.

The logic implementation schemes according to embodiments of theinvention have significant advantages compared to JJ-basedsingle-flux-quantum logic (SFQ) and reciprocal quantum logic (RQL). Oneof the main advantages includes use of voltage bias as opposed tocurrent bias in JJ-based circuits. This makes considerably less complexcircuit design and integration possible. In addition to this, since QPSJacts as an insulator, due to phase-slip, there is no current when thereare no logic pulses leading to zero-static power dissipation. Thedynamic power dissipation is orders of magnitude smaller compared toJJ-based logic. The power-delay comparison for charge-based logic,single-flux-quantum logic (SFQ) and reciprocal quantum logic (RQL) isshown in compared in the FIG. 44. These calculations are based onpractically implementable junctions and circuits. For QPSJ, the junctionparameters are calculated for well-designed junctions based on atheoretical model recently reported for phase-slip energy calculation.For Hs, popular JJ/SFQ fabrication technology parameters are consideredfor this calculation. As shown in FIG. 44, the power consumption can betwo orders of magnitude lower with comparable switching speeds. Nocomparison to CMOS based logic is made as the CMOS logic will haveseveral orders of magnitude higher power consumption along with ordersof magnitude slower switching speeds.

Using the same theoretical model of phase-slip energies used for abovecalculation, predictions are made to facilitate practical implementationof QPSJ and charge-based logic, along with CQL, of material and designparameters of the nano-wire. An example calculation is shown in FIG. 5,but several materials and design parameters (physical dimensions of thenano-wire) are considered and several calculations are made. ‘InOx’ ispredicted to the suitable material for higher probability of phase-slipswith shaded region in the FIG. 5 indicating region for highestprobability of phase-slip events, where physical dimensions of nano-wireversus a parameter with shaded region indicating highest probability ofphase-slips for InOx material.

The foregoing description of the exemplary embodiments of the presentinvention has been presented only for the purposes of illustration anddescription and is not intended to be exhaustive or to limit theinvention to the precise forms disclosed. Many modifications andvariations are possible in light of the above teaching.

The embodiments were chosen and described in order to explain theprinciples of the invention and their practical application so as toactivate others skilled in the art to utilize the invention and variousembodiments and with various modifications as are suited to theparticular use contemplated. Alternative embodiments will becomeapparent to those skilled in the art to which the present inventionpertains without departing from its spirit and scope. Accordingly, thescope of the present invention is defined by the appended claims ratherthan the foregoing description and the exemplary embodiments describedtherein.

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What is claimed is:
 1. A superconducting logic cell, comprising: atleast one quantum phase-slip junction (QPSJ) for receiving at least oneinput and responsively providing at least one output, each QPSJ beingconfigured such that when an input voltage of an input voltage pulseexceeds a critical value, a quantized charge of a Cooper electron pairtunnels across said QPSJ as an output, when the input voltage is lessthan the critical value, no quantized charge of the Cooper electron pairtunnels across said QPSJ as the output, wherein the presence and absenceof the quantized charge that is realizable as a constant area of currentpulses in the output form two logic states, and wherein the at least oneQPSJ is biased with a bias voltage.
 2. The superconducting logic cell ofclaim 1, wherein the bias voltage is about 50-95% of the criticalvoltage, the input voltage is at least about 110% of the criticalvoltage for quantized charge tunneling.
 3. The superconducting logiccell of claim 1, wherein each QPSJ is characterizable as a compactcircuit model for SPICE implementation, wherein the compact circuitmodel comprises a voltage source, a QPSJ, an inductor representing aninductance of a nano-wire of the QPSJ, and a non-linear resistor havingdifferent values of resistance in different phases of operation andshowing normal to superconductor transition as a function of the voltageacross the QPSJ, coupling to each other in series.
 4. Thesuperconducting logic cell of claim 3, wherein the critical voltage, theinductance, and the resistance are determined by material properties andphysical dimensions of the QPSJ.
 5. The superconducting logic cell ofclaim 1, wherein the at least one QPSJ comprises two QPSJs, wherein anode connecting two QPSJs and a capacitor defines a charge island. 6.The superconducting logic cell of claim 5, wherein when the quantizedcharge of the Cooper electron pair tunnels across one of the two QPSJs,the quantized charge of the Cooper electron pair is stored in the chargeisland, otherwise no quantized charge of the Cooper electron pair isstored in the charge island, thereby forming a basic logic elementhaving the two logic states.
 7. The superconducting logic cell of claim1, being a QPSJ transmission line, wherein the at least one QPSJcomprises a plurality of QPSJs connected to one another in series,wherein each node connecting two adjacent QPSJs and a capacitor definesa charge island.
 8. The superconducting logic cell of claim 7, whereinthe quantized charge of the Cooper electron pair is stored in a chargeisland or forced to hop to its immediately next charge island, by designof or tuning a capacitance of the charge island, along with the junctionparameters, thereby transferring the quantized charge of the Cooperelectron pair along the QPSJ transmission line.
 9. The superconductinglogic cell of claim 7, wherein amplification or attenuation of thecurrent pulse amplitude is obtained by using the QPSJs of differentcritical voltages and different capacitor values.
 10. Thesuperconducting logic cell of claim 1, being a QPSJ pulse splitter,wherein the at least one QPSJ comprises three QPSJs, wherein the firstQPSJ has a first terminal connected to an input voltage source definingan input node, and a second terminal connected to a first capacitor; thesecond QPSJ has a first terminal connected to the second terminal of thefirst QPSJ, and a second terminal connected to a second capacitor and afirst bias voltage source defining a first output node; and the thirdQPSJ has a first terminal connected to the second terminal of the firstQPSJ, and a second terminal connected to a third capacitor and a secondbias voltage source defining a second output node, wherein in operation,an input pulse at the input node is split into two pulses output fromthe first and second output nodes respectively.
 11. The superconductinglogic cell of claim 1, being a QPSJ buffer, wherein the at least oneQPSJ comprises three QPSJs, wherein the first QPSJ has a first terminalconnected to an input voltage source or a first bias voltage sourcedefining a first node, and a second terminal connected to a firstcapacitor defining a second node; the second QPSJ has a first terminalconnected to the second terminal of the first QPSJ defining a thirdnode, and a second terminal connected to a second capacitor and thefirst bias voltage source or the input voltage source defining a fourthnode; and the third QPSJ has a first terminal connected to the thirdnode, and a second terminal connected to a second bias voltage source,wherein in operation, an input pulse from the first node through thefirst QPSJ switches to the third QPSJ, before it switches to the secondQPSJ so as to prevent a signal flow in a direction from the first nodeto the fourth node, or when current arrives from an opposite direction,the first QPSJ switches before the third QPSJ, allowing the signalthrough.
 12. The superconducting logic cell of claim 1, being a QPSJconfluence buffer, wherein the at least one QPSJ comprises four QPSJs,wherein the first QPSJ has a first terminal connected to a first inputvoltage source, and a second terminal connected to a first capacitordefining node 3; the second QPSJ has a first terminal connected to asecond input voltage source, and a second terminal connected to a secondcapacitor defining node 6, wherein both nodes 3 and 6 are connected tonode 7; the third QPSJ has a first terminal connected to node 7, and asecond terminal connected to a first bias voltage source; and the fourthQPSJ has a first terminal connected to node 7, and a second terminalconnected to a third capacitor and the second bias voltage source atnode 8, wherein in operation, input pulses from either the first orsecond input voltage sources result in an output pulse from node 8, butdo not result in output from the other input.
 13. The superconductinglogic cell of claim 12, being a QPSJ based OR gate, wherein the at leastone QPSJ comprises six QPSJs, wherein the first to fourth QPSJs definethe confluence buffer and the fifth and sixth QPSJs define an island,wherein the confluence buffer is connected to the island in series suchthat a first terminal of the fifth QPSJ is connected to the outputterminal of the confluence buffer and a second terminal of the sixthQPSJ is connected to a clock signal of a third input voltage source thatis connected to a second bias voltage source.
 14. The superconductinglogic cell of claim 12, being a QPSJ based AND gate, wherein the atleast one QPSJ comprises five QPSJs, wherein the first to fourth QPSJsdefine the confluence buffer and the fifth QPSJ has a first terminalconnected to the output terminal of the confluence buffer and a secondterminal connected to a second bias voltage source, and the outputterminal of the confluence buffer is connected to a clock signal of athird input voltage source that is connected to a second bias voltagesource.
 15. The superconducting logic cell of claim 12, being a QPSJbased XOR gate, wherein the at least one QPSJ comprises four QPSJs,wherein the first to fourth QPSJs define the confluence buffer and theoutput terminal of the confluence buffer is connected to a clock signalof a third input voltage source that is connected to a second biasvoltage source.
 16. The superconducting logic cell of claim 1, being anRS flip-flop or a D flip-flop, wherein the at least one QPSJ comprisestwo QPSJs, wherein the first QPSJ has a first terminal connected to abias voltage source at node 2 that in turn is connected to a first inputvoltage source connected to node 1, a second terminal connected node 3that in turn is connected to a capacitor; and the second QPSJ has afirst terminal connected to node 3, and a second terminal connected tonode 4 that is in turn connected to the second input voltage source. 17.The superconducting logic cell of claim 16, being the RS flip-flop,wherein in operation, a SET input signal at node 1 induces a quantizedcharge of the Cooper electron pair to the island of node 3, and a RESETinput signal at node 4 induces a current pulse opposite to that inducedby the SET input signal so as to reset the charge on the island.
 18. Thesuperconducting logic cell of claim 16, being the D flip-flop, whereinin operation, a SET input signal at node 1 induces a quantized charge ofthe Cooper electron pair to the island of node 3, and a RESET inputsignal at node 4 is a clock signal that switches the first QPSJ andinduces a quantized charge of the Cooper electron pair on the island,and with the next clock pulse, the charge flows through an outputterminal to perform a function of the D flip-flop.
 19. Thesuperconducting logic cell of claim 1, being a T flip-flop, wherein theat least one QPSJ comprises two QPSJs, wherein the first QPSJ has afirst terminal connected to a bias voltage source at node 3 that in turnis connected to an input voltage source at node 2, the input voltagesource connected to node 1, a second terminal connected node 4 that inturn is connected to a capacitor; and the second QPSJ has a firstterminal connected to node 4, and a second terminal connected to node 2,wherein in operation, a single clock signal of the input voltage sourceis input at node 1, and at each clock pulse, the current pulse togglesfrom ON to OFF and vice versa, indicating the presence and absence of aquantized charge of the Cooper electron pair on the island with eachclock pulse.
 20. The superconducting logic cell of claim 1, furthercomprising: at least one Josephson junction (JJ) coupled with the atleast one QPSJ to perform one or more logic operations, wherein each JJis configured such that when an input current through said JJ exceeds acritical value, a single flux quantum pulse tunnels across said JJ as anoutput, when the input current is less than the critical value, nosingle flux quantum pulse tunnels across said JJ as the output, whereinthe presence and absence of the single flux quantum pulse in the outputform two logic states.
 21. The superconducting logic cell of claim 20,wherein the at least one QPSJ comprises two QPSJs defining a QPSJ islandwith a capacitor, and the at least one JJ comprises two JJs defining aJJ loop with a inductor, and the QPSJ island and the JJ loop isconnected in series to perform a bridge operation between flux andcharge.
 22. The superconducting logic cell of claim 21, wherein the atleast one QPSJ further comprises a third QPSJ having a first terminalconnected to a node between the QPSJ island and the JJ loop, and asecond terminal connected to a bias voltage source, wherein inoperation, a voltage pulse is induced through the third QPSJ thatenables or disables the output pulse.
 23. A superconducting circuitdevice, comprising: at least one superconducting logic cell, eachsuperconducting logic cell comprising: at least one quantum phase-slipjunction (QPSJ) for receiving at least one input and responsivelyproviding at least one output, each QPSJ being configured such that whenan input voltage of an input voltage pulse exceeds a critical value, aquantized charge of a Cooper electron pair tunnels across said QPSJ asan output, when the input voltage is less than the critical value, noquantized charge of the Cooper electron pair tunnels across said QPSJ asthe output, wherein the presence and absence of the quantized chargethat is realizable as a constant area of current pulses in the outputform two logic states, and wherein the at least one QPSJ is biased witha bias voltage.
 24. The superconducting circuit device of claim 23,wherein the at least one superconducting logic cell comprises a chargeisland, a QPSJ transmission line, a QPSJ pulse splitter, a QPSJ buffer,a QPSJ confluence buffer, a QPSJ based OR gate, a QPSJ based AND gate, aQPSJ based XOR gate, an RS flip-flop, a D flip-flop, a T flip-flop, NOR,NAND, or any combination thereof.
 25. The superconducting circuit deviceof claim 24, wherein the charge island is defined by a node connectingtwo QPSJs and a capacitor.
 26. The superconducting circuit device ofclaim 25, wherein the QPSJ transmission line comprises a plurality ofQPSJs connected to one another in series, wherein each node connectingtwo adjacent QPSJs and a capacitor defines the charge island.
 27. Thesuperconducting circuit device of claim 24, wherein the QPSJ pulsesplitter comprises three QPSJs, wherein the first QPSJ has a firstterminal connected to an input voltage source defining an input node,and a second terminal connected to a first capacitor; the second QPSJhas a first terminal connected to the second terminal of the first QPSJ,and a second terminal connected to a second capacitor and a first biasvoltage source defining a first output node; and the third QPSJ has afirst terminal connected to the second terminal of the first QPSJ, and asecond terminal connected to a third capacitor and a second bias voltagesource defining a second output node, wherein in operation, an inputpulse at the input node is split into two pulses output from the firstand second output nodes respectively.
 28. The superconducting circuitdevice of claim 24, wherein the QPSJ buffer comprises three QPSJs,wherein the first QPSJ has a first terminal connected to an inputvoltage source or a first bias voltage source defining a first node, anda second terminal connected to a first capacitor defining a second node;the second QPSJ has a first terminal connected to the second terminal ofthe first QPSJ defining a third node, and a second terminal connected toa second capacitor and the first bias voltage source or the inputvoltage source defining a fourth node; and the third QPSJ has a firstterminal connected to the third node, and a second terminal connected toa second bias voltage source, wherein in operation, an input pulse fromthe first node through the first QPSJ switches to the third QPSJ, beforeit switches to the second QPSJ so as to prevent a signal flow in adirection from the first node to the fourth node, or when currentarrives from an opposite direction, the first QPSJ switches before thethird QPSJ, allowing the signal through.
 29. The superconducting circuitdevice of claim 24, wherein the QPSJ confluence buffer comprises fourQPSJs, wherein the first QPSJ has a first terminal connected to a firstinput voltage source, and a second terminal connected to a firstcapacitor defining node 3; the second QPSJ has a first terminalconnected to a second input voltage source, and a second terminalconnected to a second capacitor defining node 6, wherein both nodes 3and 6 are connected to node 7; the third QPSJ has a first terminalconnected to node 7, and a second terminal connected to a first biasvoltage source; and the fourth QPSJ has a first terminal connected tonode 7, and a second terminal connected to a third capacitor and thesecond bias voltage source at node 8, wherein in operation, input pulsesfrom either the first or second input voltage sources result in anoutput pulse from node 8, but do not result in output from the otherinput.
 30. The superconducting circuit device of claim 29, wherein theQPSJ based OR gate comprises six QPSJs, wherein the first to fourthQPSJs define the confluence buffer and the fifth and sixth QPSJs definean island, wherein the confluence buffer is connected to the island inseries such that a first terminal of the fifth QPSJ is connected to theoutput terminal of the confluence buffer and a second terminal of thesixth QPSJ is connected to a clock signal of a third input voltagesource that is connected to a second bias voltage source.
 31. Thesuperconducting circuit device of claim 29, wherein the QPSJ based ANDgate comprises five QPSJs, wherein the first to fourth QPSJs define theconfluence buffer and the fifth QPSJ has a first terminal connected tothe output terminal of the confluence buffer and a second terminalconnected to a second bias voltage source, and the output terminal ofthe confluence buffer is connected to a clock signal of a third inputvoltage source that is connected to a second bias voltage source. 32.The superconducting circuit device of claim 29, wherein the QPSJ basedXOR gate comprises four QPSJs, wherein the first to fourth QPSJs definethe confluence buffer and the output terminal of the confluence bufferis connected to a clock signal of a third input voltage source that isconnected to a second bias voltage source.
 33. The superconductingcircuit device of claim 24, wherein the RS flip-flop or the D flip-flopcomprises two QPSJs, wherein the first QPSJ has a first terminalconnected to a bias voltage source at node 2 that in turn is connectedto a first input voltage source connected to node 1, a second terminalconnected node 3 that in turn is connected to a capacitor; and thesecond QPSJ has a first terminal connected to node 3, and a secondterminal connected to node 4 that is in turn connected to the secondinput voltage source.
 34. The superconducting circuit device of claim33, wherein in operation, a SET input signal at node 1 induces aquantized charge of the Cooper electron pair to the island of node 3,and a RESET input signal at node 4 induces a current pulse opposite tothat induced by the SET input signal so as to reset the charge on theisland.
 35. The superconducting circuit device of claim 33, wherein inoperation, a SET input signal at node 1 induces a quantized charge ofthe Cooper electron pair to the island of node 3, and a RESET inputsignal at node 4 is a clock signal that switches the first QPSJ andinduces a quantized charge of the Cooper electron pair on the island,and with the next clock pulse, the charge flows through an outputterminal to perform a function of the D flip-flop.
 36. Thesuperconducting circuit device of claim 24, wherein the T flip-flopcomprises two QPSJs, wherein the first QPSJ has a first terminalconnected to a bias voltage source at node 3 that in turn is connectedto an input voltage source at node 2, the input voltage source connectedto node 1, a second terminal connected node 4 that in turn is connectedto a capacitor; and the second QPSJ has a first terminal connected tonode 4, and a second terminal connected to node 2, wherein in operation,a single clock signal of the input voltage source is input at node 1,and at each clock pulse, the current pulse toggles from ON to OFF andvice versa, indicating the presence and absence of a quantized charge ofthe Cooper electron pair on the island with each clock pulse.
 37. Thesuperconducting circuit device of claim 24, being a QPSJ basedhalf-adder comprising the AND and XOR gates along with splitters tosplit the input pulses to both the XOR and AND gates.
 38. Thesuperconducting circuit device of claim 24, being a QPSJ based shiftregister comprising a plurality of stages connected in series, eachstage comprising the D flip-flop and having a different but identicalclock input.
 39. The superconducting circuit device of claim 24, being aQPSJ based ring counter comprising a plurality of stages connected toone another in a ring.
 40. The superconducting circuit device of claim24, being a QPSJ based OR-AND circuit.
 41. The superconducting circuitdevice of claim 24, being a QPSJ based ring oscillator comprising twoQPSJ transmission lines, a confluence buffer and a pulse splitter,wherein the confluence buffer is connected to the first QPSJtransmission lines that in turn is connected to the pulse splitter, thepulse splitter is connected to the second QPSJ transmission lines thatin turn is connected to the confluence buffer.
 42. The superconductingcircuit device of claim 23, further comprising at least onecomplementary quantum logic (CQL) cell, each CQL cell comprising atleast one QPSJ, and at least one Josephson junction (JJ) coupled withthe at least one QPSJ to perform one or more logic operations, whereineach JJ is configured such that when an input current through said JJexceeds a critical value, a single flux quantum pulse tunnels acrosssaid JJ as an output, when the input current is less than the criticalvalue, no single flux quantum pulse tunnels across said JJ as theoutput, wherein the presence and absence of the single flux quantumpulse in the output form two logic states.
 43. The superconductingcircuit device of claim 42, wherein the CQL cell comprises two QPSJsdefining a QPSJ island with a capacitor, and two JJs defining a JJ loopwith a inductor, and the QPSJ island and the JJ loop is connected inseries to perform a bridge operation between flux and charge.
 44. Thesuperconducting circuit device of claim 43, wherein the CQL cell furthercomprises a third QPSJ having a first terminal connected to a nodebetween the QPSJ island and the JJ loop, and a second terminal connectedto a bias voltage source, wherein in operation, a voltage pulse isinduced through the third QPSJ that enables or disables the outputpulse.
 45. A superconducting circuit device, comprising at least one ofone or more Josephson junctions and one or more quantum phase slipjunctions.